Chip package process

Patent metadata

Field	Value
Publication number	US-11081371-B2
Application number	US-201715636646-A
Country	US
Kind code	B2
Filing date	Jun 29, 2017
Priority date	Aug 29, 2016
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. An encapsulated material is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the encapsulated material and the carrier plate. The encapsulated material is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.

First claim

What is claimed is:

1. A chip package process, comprising:
providing a supporting structure and a carrier plate, wherein the supporting structure has a plurality of openings, the supporting structure is disposed on the carrier plate, and the supporting structure is a continuous reticular structure;
disposing a plurality of chips on the carrier plate, wherein the chips are respectively located in the openings of the supporting structure, each chip has an active surface, and the active surface is directly disposed on the carrier plate;
forming an encapsulated material covering the supporting structure and the chips, wherein the supporting structure and the chips are located between the encapsulated material and the carrier plate, and the encapsulated material is filled between the openings and the chips;
removing an entire part of the carrier plate;
disposing a redistribution structure on the supporting structure, wherein the redistribution structure is connected to the chips, the supporting structure and the redistribution structure are substantially in contact with each other, and the entire supporting structure and the redistribution structure are electrically insulated from each other, wherein the reticular structure includes a single layer with a plurality of rectangular openings, and the chips are respectively located in the plurality of rectangular openings; and
removing a portion of the encapsulated material to expose the chips, wherein, after the portion of the encapsulated material is removed, the supporting structure, the chips, and the encapsulated material are coplanar.

2. The chip package process of claim 1 , wherein in the step of removing the carrier plate, the supporting structure, the chips, and the encapsulated material form a common plane.

3. The chip package process of claim 1 , wherein in the step of disposing a redistribution structure on the supporting structure, each of the chips comprises at least one pad, and the redistribution structure is directly connected to the pads.

4. The chip package process of claim 1 , further comprising:
cutting the supporting structure and the redistribution structure along a plurality of cutting lines between the openings to form a plurality of chip packages, wherein the supporting structure after cutting comprises a top surface and a bottom surface opposite to the top surface, a first side surface connected with a first end of each of the top surface and the bottom surface and a second side surface connected with a second end of each of the top surface and the bottom surface, and a maximum width from the first side surface to the second side surface is greater than a maximum thickness from the top surface to the bottom surface.

5. The chip package process of claim 4 , wherein a portion of the supporting structure is exposed at a side of the corresponding chip package.

6. The chip package process of claim 1 , wherein the supporting structure has at least one inner surface in each of the openings, the at least one inner surface has at least one groove, and the encapsulated material is completely filled in the at least one groove.

7. The chip package process of claim 1 , wherein the supporting structure has at least one inner surface in each of the openings, and the at least one inner surface is inclined in a direction away from the chips such that the encapsulated material is extended above the inner surface, and the at least one inner surface is not vertical to a top surface of the supporting structure away from the redistribution structure.

8. The chip package process of claim 1 , wherein the step of disposing the plurality of chips on the carrier plate comprises:
disposing a plurality of passive elements on the carrier plate, wherein the encapsulated material completely covers the passive elements.

9. The chip package process of claim 4 , wherein the supporting structure is one annular supporting member for each of the chip packages.

10. The chip package process of claim 1 , further comprising:
removing a portion of the encapsulated material located on the supporting structure and only keeping the encapsulated material located between the supporting structure and the chips.

11. The chip package process of claim 1 , wherein the supporting structure is not located between the chips and the redistribution structure.

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Chang Wen-Yuan
• Chen Wei-Cheng
• Lu Hsueh-Chung Shelton

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/0198

  batch processes · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title