Exposed die quad flat no-leads (qfn) package

Patent metadata

Field	Value
Publication number	US-2016005679-A1
Application number	US-201414322419-A
Country	US
Kind code	A1
Filing date	Jul 2, 2014
Priority date	Jul 2, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

Consistent with an example embodiment, there is a method for packaging an integrated circuit (IC) device. The method comprises attaching a lead frame to the carrier tape; the lead frame has an array of device positions on the carrier tape and pad landings surround the device positions for making electrical connections to the plurality of active device die. A plurality of active device die are mounted on the carrier tape within the array of device positions; each said active device die has bond pads, each of said active device die has been subjected to back-grinding to a prescribed thickness and has a solderable conductive surface on its underside. On the bond pads, the plurality of active devices are wire bonded to the pad landings on the lead frame. The lead frame and wire bonded active devices are encapsulated, leaving the solderable die backside and lead frame backside exposed.

First claim

1 - 3 . (canceled)

4 . The method as recited in claim 8 , wherein the solderable conductive surface includes alloys of: NiAu, Ni, Cu, Au, NiPdAu, AuSn, NiSn, CuSn, Ag, AgSn or combinations thereof.

5 . The method as recited in claim 4 , wherein the solderable conductive surface further includes an adhesion layer of Ti or Cr as a first layer on the under-side.

6 - 7 . (canceled)

8 . A method for packaging an integrated circuit (IC) device from a semiconductor wafer substrate, the wafer substrate having a top-side surface with a plurality active device die defined thereon, and an under-side surface, the method comprising:
back-grinding the under-side surface of the wafer substrate to a prescribed thickness; applying a solderable conductive surface to the under-side surface of the wafer substrate; separating out the plurality active device die from the semiconductor wafer substrate, each of the active device die having bond pads, the bond pads providing electrical connection to circuit elements in the active device die; and attaching the active device to a package assembly.

9 . The method as recited in claim 8 , further comprising,
attaching the package assembly to a carrier tape, the package assembly having an array of device positions on the carrier tape and pad landings surrounding the device positions for making electrical connections to the plurality of active device die;
wherein solderable conductive under-side surfaces of the plurality of the active device die have been mounted onto the carrier tape within the array of the device positions; and
conductively bonding the plurality of active device to the pad landings on the lead frame; and encapsulating the lead frame and the conductively bonded active devices;
wherein conductive bonding includes wire bonding, ribbon bonding, or a combination thereof.

10 . The method as recited in claim 9 , wherein the prescribed wafer thickness after back-grinding is less than about 50 μm.

11 . The method as recited in claim 9 , wherein the prescribed wafer thickness after back-grinding is in the range of about 50 μm to about 200 μm.

12 . The method as recited in claim 9 , wherein the package assembly is selected from one of the following package types: QFN, SMD, BGA, aQFN, LLGA, TLA, EFLGA, TLEM, HLA, or eWLB.

13 . The method as recited in claim 12 , wherein the carrier tape is further supported by a temporary carrier strip.

14 . A metal oxide silicon field effect transistor (MOSFET) integrated circuit (IC) device assembled in a QFN package, the IC comprising:
an active device die having a Pb-free solderable conductive surface on its under-side and having been subjected to back-grinding to a prescribed thickness and a top side surface, the active device die having a drain, source, and gate;
wherein the drain is connectable via the underside surface;
a lead frame assembly surrounding the active device die, the lead frame assembly having pad landings on top-side surfaces and corresponding under-side surfaces opposite the top-side surface, the source and gate of the active device die connected to respective pad landings on the top-side surface of the lead frame assembly; an encapsulant enveloping the active device die and lead frame assembly; and wherein the Pb-free solderable conductive surface and under-side surfaces of the lead frame assembly are exposed and coplanar with one another.

15 . The MOSFET IC as recited in claim 14 , wherein the source and gate are connected to respective pad landings with either wire bonds or ribbon bonds.

Assignees

• Nxp Bv

Inventors

• Israel Emil Casey
• Van Gemert Leonardus Antonius Elisabeth
• Groenhuis Roelf Anco Jacob

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title