Semiconductor structure having a group iii-v semiconductor layer comprising a hexagonal mesh crystalline structure

Patent metadata

Field	Value
Publication number	US-11081346-B2
Application number	US-201515527466-A
Country	US
Kind code	B2
Filing date	Nov 17, 2015
Priority date	Nov 18, 2014
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A semiconductor structure (100) comprising:a substrate (102),a first layer (106) of AlxGayIn(1-x-y)N disposed on the substrate,stacks (107, 109) of several second and third layers (108, 110) alternating against each other, between the substrate and the first layer,a fourth layer (112) of AlxGayIn(1-x-y)N, between the stacks,a relaxation layer of AIN disposed between the fourth layer and one of the stacks, and, in each of the stacks:the level of Ga of the second layers increases from one layer to the next in a direction from the substrate to the first layer,the level of Ga of the third layers is constant or decreasing from one layer to the next in said direction, the average mesh parameter of each group of adjacent second and third layers increasing from one group to the next in said direction,the thickness of the second and third layers is less than 5 nm.

First claim

The invention claimed is:

1. A semiconductor structure comprising:
a substrate,
a first semiconductor layer, wherein a material of the substrate and a semiconductor of the first semiconductor layer are crystalline materials having in-plane lattice parameters and the first semiconductor layer is arranged on the substrate such that in-plane lattice parameters of the first semiconductor layer are not the same as in-plane lattice parameters of the material of the substrate,
first and second stacks each comprising a plurality of second and third layers, wherein the second and third layers are arranged such that within said first and second stack a pair of second layers sandwich at least one third layer and a pair of third layers sandwich at least one second layer and the plurality of second and third layers comprise a semiconductor, the first stack being located between the substrate and the first semiconductor layer, and the second stack being located between the first stack and the first semiconductor layer,
a fourth semiconductor layer with similar or approximately the same composition as the semiconductor in the first semiconductor layer and located between the first and the second stacks,
a relaxation layer consisting of AIN and located between the fourth semiconductor layer and the second stack,
wherein the semiconductors in the first semiconductor layer, the second layers, the third layers, and the fourth semiconductor layer has the formula Al x Ga y In (1-x-y) N, where 0<X<1, 0<Y <1 and (X+Y) 1,
and in each of the first and the second stacks:
the ratio of Ga in the semiconductor in the second layers varies and increases from one second layer to the next along a direction from the substrate to the first semiconductor layer,
the ratio of Ga in the semiconductor in the third layers is constant or varies and decreases from one third layer to the next along the direction from the substrate to the first semiconductor layer such that an average in-plane lattice parameter of each group of a second layer and an adjacent third layer increases from one group to the next in the first stack along said direction from the substrate to the first semiconductor layer,
the thickness of each of the second and third layers is less than about 5 nm, and each second layer is in direct contact with at least one of the third layers

wherein at least one of the following conditions is met: (i) each of the second layers comprises a uniform Ga content or (ii) except for the top most second layer, each second layer is in direct contact with two third layers on opposite sides of each of the second layers, and
wherein
the first stack is in physical or direct contact with the fourth semiconductor layer, or
the second stack is in physical or direct contact with the relaxation layer, or
the first stack is in physical or direct contact with the fourth semiconductor layer and the second stack is in physical or direct contact with the relaxation layer, or
the first stack is in direct contact with the fourth semiconductor layer, the fourth semiconductor layer is in direct contact with the relaxation layer, and the relaxation layer is in direct contact with the second stack.

2. The semiconductor structure according to claim 1 , wherein the thickness of the fourth semiconductor layer is between about 0.5 and 1.5 times the thickness of the first stack.

3. The semiconductor structure according to claim 1 , wherein the semiconductor in the first semiconductor layer is GaN, and/or the semiconductor in the second layers is Al x Ga (1-x) N, and/or the semiconductor in the third layers is GaN.

4. The semiconductor structure according to claim 1 , wherein, in each of the first and second stacks, the semiconductor in the second layers is Al x Ga (1-x) N such that X varies from about 1 to about 0.3 from one second layer to the next along the direction from the substrate to the first semiconductor layer.

5. The semiconductor structure according to claim 1 , further comprising a first buffer layer comprising AlN and located between the substrate and the first stack.

6. The semiconductor structure according to claim 1 , wherein the thickness of each of the second and third layers is less than about 2 nm.

7. The semiconductor structure according to claim 1 , wherein the thicknesses of all of the second layers are similar and/or the thicknesses of all of the third layers are similar.

8. The semiconductor structure according to claim 1 , wherein the substrate comprises monocrystalline silicon.

9. The semiconductor structure according to claim 1 , wherein the total thickness of the first stack and/or the total thickness of the second stack is less than or equal to about 5 μm.

10. A method of making the semiconductor structure according to claim 1 , comprising making at least the first semiconductor layer, the second layer, the third layer and the fourth semiconductor layer and the relaxation layer by molecular beam epitaxy or by vapor phase epitaxy.

11. A semiconductor device corresponding to a light emitting diode or a transistor, said semiconductor device comprising the semiconductor structure according to claim 1 and an active zone which includes the first semiconductor layer of the semiconductor structure located on the first semiconductor layer of the semiconducting structure.

12. The semiconductor structure according to claim 1 , wherein each of the second layers comprises a uniform Ga content.

13. The semiconductor structure according to claim 1 , wherein except for the top most second layer, each second layer is in direct contact with two third layers on opposite sides of each of the second layers.

14. The semiconductor structure according to claim 1 , wherein each of the second layers comprises a uniform Ga content and except for the top most second layer, each second layer is in direct contact with two third layers on opposite sides of each of the second layers.

Assignees

• Commissariat Energie Atomique

Inventors

• Charles Matthew

Classifications

• H10P14/3424

  being Group IIB-VIA materials · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/3254

  Graded layers · CPC title

• H10P14/3221

  Arsenides · CPC title