Write training in memory devices

Patent metadata

Field	Value
Publication number	US-11079946-B2
Application number	US-201816171442-A
Country	US
Kind code	B2
Filing date	Oct 26, 2018
Priority date	Oct 26, 2018
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.

First claim

What is claimed is:

1. A memory die comprising:
a plurality of input/output (I/O) nodes to receive a periodic predefined data pattern;
a data strobe node to receive a data strobe signal;
a delay circuit coupled to the I/O nodes to delay the data received on each I/O node based on a trim value for each I/O node;
a latch coupled to the delay circuit to latch the delayed data for each I/O node in response to the data strobe signal;
a cache register to store the latched data;
a state machine to change the trim value for each I/O node after each period of the predefined data pattern is received; and
a controller to select the trim value for each I/O node based on a comparison between the stored data and an expected data pattern for each I/O node;
wherein the controller is to generate a table indicating which stored data for each I/O node for each period of the predefined data pattern matches the expected data pattern for each I/O node and which stored data for each I/O node for each period of the predefined data pattern does not match the expected data pattern for each I/O node, and
wherein the controller selects the trim value for each I/O node based on the table.

2. The memory die of claim 1 , further comprising:
a deserializer coupled between the latch and the cache register to convert serial data from the latch to parallel data for storage in the cache register.

3. The memory die of claim 1 , further comprising:
an XOR circuit to compare the stored data to the expected data pattern for each I/O node.

4. The memory die of claim 1 , wherein the controller comprises a pattern generator to generate the expected data pattern for each I/O node.

5. The memory die of claim 1 , wherein the controller selects the trim value for each I/O node to adjust the setup and hold time margin for each I/O node.

6. The memory die of claim 1 , wherein the state machine is to sweep a predetermined number of trim values for each I/O node.

7. The memory die of claim 6 , wherein the predetermined number equals 16.

8. The memory die of claim 1 , wherein the delay circuit is coupled to the data strobe node to delay the data strobe signal based on a trim value for the data strobe signal,
wherein the state machine is to change the trim value for the data strobe signal after a plurality of periods of the predefined data pattern is received; and
wherein the controller is to select the trim value for the data strobe signal based on a comparison between the stored data and the expected data pattern for each I/O node.

9. The memory device of claim 1 , wherein the controller is to compare the stored data to the expected data pattern for each I/O node to generate the table.

10. A memory system comprising:
a host to provide a periodic predefined data pattern and a data strobe signal; and
a first memory die coupled to the host, the first memory die comprising:
a plurality of input/output (I/O) nodes to receive the periodic predefined data pattern;
a data strobe node to receive the data strobe signal;
a delay circuit to adjust a delay of data received by each I/O node based on a trim value for each I/O node and to adjust a delay of the data strobe signal based on a trim value for the data strobe node;
a latch to latch the data received by each I/O node in response to the data strobe signal; and
a controller to compare the latched data to an expected data pattern and to set the trim value for each I/O node and the trim value for the data strobe signal based on the comparison;
wherein the controller is to compare the latched data to the expected data pattern to generate a table indicating which latched data matches the expected data pattern and which latched data does not match the expected data pattern, and
wherein the controller sets the trim value for each I/O node based on the table.

11. The memory system of claim 10 , further comprising:
a second memory die coupled to the host, the second memory die comprising:
a plurality of input/output (I/O) nodes to receive the periodic predefined data pattern;
a data strobe node to receive the data strobe signal;
a delay circuit to adjust a delay of data received by each I/O node based on a trim value for each I/O node and to adjust a delay of the data strobe signal based on a trim value for the data strobe node;
a latch to latch the data received by each I/O node in response to the data strobe signal; and
a controller to compare the latched data to an expected data pattern and to set the trim value for each I/O node and the trim value for the data strobe signal based on the comparison.

12. The memory system of claim 10 , wherein the controller generates the expected data pattern.

13. The memory system of claim 10 , wherein the first memory die comprises a NAND memory.

14. A method for write training in a memory system, the method comprising:
loading, via a host, a periodic predefined data pattern to a plurality of input/output (I/O) nodes of a first memory die;
changing, within the first memory die, a trim value of a delay for each I/O node of the first memory die after each period of the predefined data pattern;
latching, within the first memory die, the delayed data for each I/O node of the first memory die;
comparing, within the first memory die, the latched data for each I/O node of the first memory die to an expected data pattern;
setting, within the first memory die, the trim value of the delay for each I/O node of the first memory die based on the comparison; and
generating a table indicating which latched data for each I/O node of the first memory die matches the expected data pattern and which latched data for each I/O node of the first memory die does not match the expected data pattern;
wherein setting the trim value of the delay for each I/O node of the first memory die comprises setting the trim value of the delay for each I/O node of the first memory die based on the table.

15. The method of claim 14 , further comprising:
loading, via the host and simultaneously with loading the periodic predefined data pattern to the plurality of I/O nodes of the first memory die, the periodic predefined data pattern to a plurality of input/output (I/O) nodes of a second memory die;
changing, within the second memory die, a trim value of a delay for each I/O node of the second memory die after each period of the predefined data pattern;
latching, within the second memory die, the delayed data for each I/O node of the second memory die;
comparing, within the second memory die, the latched data for each I/O node of the second memory die to an expected data pattern; and
setting, within the second memory die, the trim value of the delay for each I/O node of the second memory die based on the comparison.

16. The method of claim 14 , further comprising:
providing, via the host, a data strobe signal to a data strobe node of the first memory die;
changing, within the first memory die, a trim value of a delay for the data strobe signal of the first memory die after a plurality of periods of the predefined data pattern;
latching, within the first memory die, the delayed data for each I/O node of the first memory die in response to the data strobe signal of the first memory die; and
setting, within the first memory die, the trim value of the delay for the data strobe signal of the first memory die based on the comparison.

17. The method of claim 14 , wherein changing, within the first memory die, the trim value comprises incrementing the trim value after each period of the predefined data pattern, the trim value starting

Assignees

• Micron Technology Inc

Inventors

• Pilolli Luigi
• Feiz Zarrin Ghalam Ali
• Wang Guan
• Tang Qiang

Classifications

• G11C2029/3602

  Pattern generator · CPC title

• G11C2029/2602

  Concurrent test · CPC title

• G11C2029/1206

  Location of test circuitry on chip or wafer · CPC title

• G11C29/36

  Data generation devices, e.g. data inverters · CPC title

• G11C29/26

  Accessing multiple arrays (G11C29/24 takes precedence) · CPC title