Apparatuses and methods for timing provision of a command to input circuitry

Patent metadata

Field	Value
Publication number	US-9530473-B2
Application number	US-201414285476-A
Country	US
Kind code	B2
Filing date	May 22, 2014
Priority date	May 22, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

An apparatus or method may include provision of a command to a data block. An example apparatus includes a command circuit configured to provide a command signal in an internal clock time domain based at least in part on a memory access command received in an external clock time domain. The example apparatus further includes a command path delay configured to delay the command signal. The example apparatus further includes a data strobe generator circuit configured to receive the command signal and a data strobe signal. A plurality of clock edges of the data strobe signal correspond to received data bits associated with the memory access command. The data strobe generator circuit is configured to control input circuitry to capture the data associated with the memory access command based at least in part on the data strobe signal and the command signal.

First claim

What is claimed is:

1. An apparatus, comprising:
a command circuit configured to provide a command signal in an internal clock time domain based at least in part on a memory access command received in an external clock time domain;
a command path delay configured to delay the command signal;
a strobe generator circuit configured to receive the delayed command signal and a strobe signal, wherein a plurality of clock edges of the strobe signal correspond to received data associated with the memory access command, the strobe generator circuit configured to control input circuitry to capture the data associated with the memory access command based at least in part on the strobe signal and the delayed command signal, wherein the strobe generator circuit comprises logic configured to generate a pulse beginning at a clock edge of the strobe signal corresponding to a first bit of the data and ending at a clock edge of the strobe signal corresponding to a last bit of the data.

2. The apparatus of claim 1 , wherein the strobe generator circuit comprises logic that prevents the input circuit from capturing data between consecutive memory access commands.

3. The apparatus of claim 1 , wherein the strobe generator circuit comprises:
a first latch configured to receive the delayed command signal and the strobe signal, the first latch configured to provide a preamble command signal at an output by propagating the delayed command signal through the first latch based at least in part on the strobe signal;
a second latch configured to receive the preamble command signal from the first latch and the strobe signal, the second latch configured to provide a postamble command signal at an output by propagating the preamble command signal through the second latch based at least in part on the strobe signal; and
a first logic gate configured to receive the preamble command signal and the postamble command signal, the logic gate configured to provide a write data signal at an output based at least in part on a logical OR comparison of the preamble command signal and the postamble command signal.

4. The apparatus of claim 3 , further comprising:
counter circuits configured to count clock edges of the strobe signal associated with bits of the data associated with the memory access command, the counter circuits configured to provide an output signal based at least in part on a count of bits in a burst of data;
a pulse generator configured to provide a write pulse based at least in part on the output signal;
a second logic gate configured to provide flip-flop input signal to at an output based at least in part on a NAND logic comparison between an the write pulse and an inverted value of the write data signal;
a flip-flop configured to receive the write pulse and the preamble command signal, based at least in part on the strobe signal, the flip-flop configured to provide a write burst signal at an output based at least in part on the preamble command signal and the write pulse; and
a third logic gate configured to provide an empty cycle signal at an output based at least in part on a NAND logic comparison between an inverted write data signal and the write burst signal; and
reset logic circuits configured to receive the empty cycle signal and to prevent the counter circuits from counting responsive to the empty cycle signal having a value indicating an empty cycle.

5. The apparatus of claim 1 , wherein the memory access command is a write command, and wherein the data is write data.

6. The apparatus of claim 3 , wherein the command circuit is configured to generate the write data signal having a pulse width equal to a count of clock cycles of the internal clock equal to half a number of bits in a data burst.

7. The apparatus of claim 6 , wherein the number of bits in the data burst is 8 bits and the pulse width is equal to 4 clock cycles of the internal clock or the number of bits in the data burst is 4 bits and the pulse width is equal to 2 clock cycles.

8. An apparatus, comprising:
a command circuit configured to receive a memory access command in a time domain of an external clock signal, the command circuit configured to provide an internal command signal in a time domain of an internal clock signal, wherein the internal command signal includes a pulse having a width equal to a number of clock cycles of the internal clock signal equal to half of a number of bits of data associated with the memory access command, wherein the internal clock signal is delayed relative to the external clock signal based at least in part on a propagation delay a clock path;
input circuitry configured to receive the data associated with the memory access command;
a command delay path configured to delay the internal command signal, wherein the delay of the command delay path is based at least in part on the propagation delay through at least a portion of the clock path; and
a data strobe generator circuit configured to receive the internal command signal delayed from the command delay path, the data strobe generator circuit further configured to receive a data strobe signal, wherein clock edges of the data strobe signal correspond to individual bits of the data, wherein the start of the pulse of the internal command signal is received at the data strobe generator circuit prior to a clock edge of the data strobe signal corresponding to a first bit of the data, the data strobe generator circuit configured to control the input circuitry to capture the data.

9. The apparatus of claim 8 , further comprising a data strobe command circuit coupled between the command circuit and the command delay path, the data strobe command circuit configured to apply a synchronous delay to the internal command signal.

10. The apparatus of claim 8 , further comprising a clock generator configured to delay the external clock signal to provide the internal clock signal; wherein the delay is based at least in part on a propagation delay through the clock path.

11. The apparatus of claim 10 , further comprising:
an input buffer configured to receive the data strobe signal; and
a clock tree circuit configured to provide the data strobe signal from the input buffer to the data strobe generator circuit, wherein the delay through the command delay path is further based at least in part on a propagation delay through the clock tree circuit.

12. The apparatus of claim 11 , wherein the delay through the command delay path is further based at least in part on the propagation delay through an output buffer and the propagation delay through the input buffer.

13. The apparatus of claim 8 , wherein the delay through the command delay path is an asynchronous delay.

14. The apparatus of claim 8 , wherein the command delay path is configured to delay the internal command signal such that the pulse of the internal command signal is received at the data strobe generator circuit between one-fourth of a clock cycle of the data strobe signal prior to receiving the clock edge of the data strobe signal corresponding to the first bit of the data and three-quarters of the clock cycle of the data strobe signal prior to receiving the clock edge of the data strobe signal corresponding to the first bit of the data.

15. The apparatus of claim 8 , wherein the data strobe generator circuit comprises logic circuits configured to generate control signals based at least in part on the data strobe signal and the internal command signal, wherein the control signals are provided to the input circuit to capture the data.

16. The apparatus of claim 8 , wherein the command delay path comprises a dela

Assignees

• Micron Technology Inc

Inventors

• Mazumder Kallol

Classifications

• G11C7/225

  Clock input buffers · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/106

  Data output latches · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/109

  Control signal input circuits · CPC title