Methods and apparatuses including command delay adjustment circuit

Patent metadata

Field	Value
Publication number	US-9865317-B2
Application number	US-201615139102-A
Country	US
Kind code	B2
Filing date	Apr 26, 2016
Priority date	Apr 26, 2016
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

First claim

What is claimed is:

1. An apparatus comprising:
a first circuit configured to respond to a first clock signal to latch a first signal, the first circuit being configured to provide a second signal; and
a second circuit coupled to the first circuit to latch the second signal, the second circuit being configured to provide a third signal based on the second signal in response to a first output timing signal that is substantially in phase to the first clock signal;
a first delay circuit configured to receive a second clock signal that is substantially in phase to the first clock signal and provide a third clock signal by delaying the second clock signal by a first delay that is adjustable;
a second delay circuit coupled to the second circuit and configured to delay the third signal by a second delay that is adjustable to provide a fourth signal;
a delay control circuit configured to adjust the first delay of the first circuit and the second delay of the second delay circuit to be substantially equal to each other;
a third circuit coupled to the second delay circuit and configured to delay the fourth signal in response to the third clock signal and latency information to provide a fifth signal; and
an output buffer coupled to the third circuit and configured to be activated in response to the fifth signal and operate in response to the third clock signal.

2. An apparatus comprising:
a first circuit configured to respond to a first clock signal to latch a first signal, the first circuit being configured to provide a second signal; and
a second circuit coupled to the first circuit to latch the second signal, the second circuit being configured to provide a third signal based on the second signal in response to a first output timing signal that is substantially in phase to the first clock signal;
wherein the second circuit is further configured to latch the second signal in response to a first input signal that is delayed in phase from the first clock signal; and
wherein the second circuit further comprises:
a counter circuit configured to receive the first clock signal and further configured to provide a plurality of timing control signals in response to the first clock signal;
a third delay circuit coupled to the counter circuit and configured to provide a plurality of second input timing signals by delaying the timing control signals;
a first decoder coupled to the third delay circuit and configured to provide a first input timing signal by decoding the second input timing signals; and
a second decoder coupled to the counter circuit and configured to provide the first output timing signal by decoding the timing control signals.

3. The apparatus as claimed in claim 2 , wherein the third delay circuit is configured to represent a first delay that is substantially constant.

4. The apparatus as claimed in claim 2 , wherein
the first decoder is further configured to provide a third input timing signal by decoding the second input timing signals,
wherein the second decoder is further configured to provide a second output timing signal by decoding the timing control signals, and
wherein the second circuit further comprises:
first and second input latch circuits coupled in common to the first circuit and configured to latch the second signal in response to the first input timing signal and the second input timing signal, respectively;
first and second output latch circuits coupled to the first and second input latch circuit and configured to output the third signal in response to the first output timing signal and the second output timing signal, respectively; and
a selector circuit including first and second input nodes coupled respectively to the first and second input latch circuits and first and second output nodes coupled respectively to the first and second output latch circuits, the selector circuit being configured to connect the first and second input latch circuits to the first and second output latch circuit in response to a selector control signal.

5. The apparatus as claimed in claim 4 , further comprising:
a third circuit coupled to the second circuit and configured to provide the selector control signal in response to a latency information.

6. An apparatus comprising:
a clock input buffer configured to provide a reference clock signal and a system clock signal based on an external clock signal;
a command decoder configured to latch command signals responsive to the system clock signal and further configured to provide a signal based on the command signals; and
a command delay adjustment circuit comprising:
a clock synchronizing circuit configured to receive the signal from the command decoder, the clock synchronizing circuit configured to latch the signal responsive to the system clock signal and further configured to provide a clock-synchronized read signal responsive to a shift cycle parameter, wherein the clock synchronizing circuit comprises:
a counter circuit configured to receive the system clock signal and further configured to provide a plurality of first timing control signals responsive to the system clock signal;
a delay circuit coupled to the counter circuit and configured to provide a plurality of second timing control signals that has a predetermined delay from the system clock signal;
a first decoder circuit coupled to the delay circuit and configured to provide pointer input signals by decoding the plurality of second timing control signals; and
a second decoder circuit coupled to the counter circuit and configured to receive the system clock signal and the plurality of first timing control signals, and further configured to provide pointer output signals by decoding the plurality of first timing control signals responsive to the system clock signal,

wherein the clock synchronizing circuit is further configured to latch the signal from the command decoder responsive to one of pointer input signals having a delay from the system clock signal.

7. The apparatus of claim 6 , wherein the clock synchronizing circuit further comprises:
an input pointer register comprising a plurality of cells, each cell comprises:
a first latch configured to receive the signal from the command decoder and a corresponding one of the pointer input signals; and
a second latch configured to receive the corresponding one of the pointer input signals and an output signal from the first latch; and

an output pointer register comprising a plurality of cells, each cell comprises:
a third latch configured to provide an output signal responsive to a corresponding one of the pointer output signals; and

a fourth latch configured to receive the corresponding one of the pointer output signals and the output signal from the third latch; and
a selector circuit comprising a plurality of input nodes coupled to the corresponding plurality of cells of the input pointer register and a plurality of output nodes coupled to the corresponding plurality of cells of the output pointer register,
wherein the selector circuit is configured to selectively couple one cell of the plurality of cells of the input pointer register to a corresponding one cell of the plurality cells of the output pointer register responsive to a selector control signal.

8. A method comprising:
providing a reference clock signal and a system clock signal based on an external clock signal in a clock input buffer;
latching command signals responsive to the system clock signal;
providing a signal based on the command signals;
latching the signal responsive to the system clock signal; and
providing a clock-synchronized read signal responsive to a shift cycle parameter responsive to latency information,
wherein latching command signals responsive to the system c

Assignees

• Micron Technology Inc

Inventors

• Ishibashi Shuichi
• Miyano Kazutaka
• Fujisawa Hiroki

Classifications

• G11C2207/2254

  Calibration · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C2207/2272

  Latency related aspects · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title