Adjustable high resolution timer

Patent metadata

Field	Value
Publication number	US-11075743-B2
Application number	US-202017004541-A
Country	US
Kind code	B2
Filing date	Aug 27, 2020
Priority date	Aug 27, 2019
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

An adjustable high resolution timer ( 100 ) for synchronizing a local clock to an external reference clock includes frequency offset acquisition and compensation unit ( 110 ) configured to acquire a frequency offset difference between the local and external reference clock and to generate frequency adjustment signals based on the frequency offset difference; a time drift tracking and adjustment unit ( 120 ) configured to continuously monitor the local and external reference clocks for phase offset differences therebetween and to generate timing adjustment signals based on the phase offset difference; a nanosecond timer core unit ( 140 ) configured to generate a frequency and phase adjusted nanosecond timer output signal in response to the frequency adjustment signals and timing adjustment signals; and a pulse generation unit ( 130 ) for generating a plurality of output pulse signals that are synchronized with the external reference clock in response to the frequency and phase adjusted nanosecond timer output signal.

First claim

What is claimed is:

1. An adjustable timer for synchronizing a local clock to an external reference clock, comprising:
a frequency offset acquisition and compensation circuitry configured to acquire a frequency offset difference between the local clock and the external reference clock, and to generate frequency adjustment signals based on the frequency offset difference;
a time drift tracking and adjustment circuitry configured to continuously monitor the local clock and external reference clock for phase offset difference between the local clock and the external reference clock and to generate timing adjustment signals based on the phase offset difference;
a nanosecond timer core circuitry configured to generate a frequency and phase adjusted nanosecond timer output signal in response to the frequency adjustment signals and timing adjustment signals; and
a pulse generation circuitry for generating a plurality of output pulse signals that are synchronized with the external reference clock in response to the frequency and phase adjusted nanosecond timer output signal.

2. The adjustable timer of claim 1 , where the frequency offset acquisition and compensation circuitry comprises:
a frequency offset acquisition circuitry configured to detect the frequency offset difference between a local clock frequency and an external reference clock frequency;
a frequency offset compensation circuitry configured to generate the frequency adjustment signals by generating a frequency compensation enable signal and nanosecond adjustment signal for adjusting a clock period input to an accumulator at the nanosecond timer core circuitry; and
a frequency offset tracking circuitry configured to continuously monitor residue frequency offset between the local clock and external reference clock after frequency offsets compensation.

3. The adjustable timer of claim 1 , where the time drift tracking and adjustment circuitry comprises:
a drift tracking circuitry configured to continuously monitor the phase offset difference between the local clock phase and the external reference clock phase and to generate a timer offset signal as one of the timing adjustment signals; and
a timing setting circuitry configured to generate additional timing adjustment signals by generating a time adjustment enable signal to enable time adjustment, a first adjustment signal for adjusting the nanosecond timer output signal for timing drift, and a second adjustment signal for setting a time value.

4. The adjustable timer of claim 1 , where the nanosecond timer core circuitry comprises:
a nanosecond timer driven by the local clock to generate a nanosecond timer output signal;
a first timer adjustment circuit for adjusting the nanosecond timer output signal in response to the frequency adjustment signals; and
a second timer adjustment circuit for adjusting the nanosecond timer output to compensate for timing drift in response to the timing adjustment signals.

5. The adjustable timer of claim 4 , where the nanosecond timer comprises an accumulator driven by a local clock period input signal to generate the nanosecond timer output signal.

6. The adjustable timer of claim 5 , where the first timer adjustment circuit comprises:
a first adder circuit connected to add the local clock period input signal with a first adjustment signal to form an increment value; and
a first multiplexer for selectively connecting the increment value or the local clock period input signal as a first input to the accumulator in response to the frequency adjustment signals.

7. The adjustable timer of claim 6 , where the second timer adjustment circuit comprises:
a second adder circuit connected to add the frequency and phase adjusted nanosecond timer output signal with a second adjustment signal to form an incremental phase adjustment value; and
a second multiplexer for selectively connecting the incremental phase adjustment or the frequency and phase adjusted nanosecond timer output signal as a second input to the accumulator in response to the timing adjustment signals.

8. The adjustable timer of claim 1 , where the nanosecond timer core circuitry comprises a timer loading and wrapping control circuitry configured to load a timer value register with an absolute timer value or normal timer wrap-around in response to the timing adjustment signals.

9. The timer control method for synchronizing a local clock to an external reference clock, comprising:
receiving a local clock as an input to an adjustable timer;
acquiring a frequency offset difference between the input local clock and the external reference clock;
generating a plurality of frequency adjustment signals to compensate for the frequency offset difference;
generating a frequency and phase adjusted nanosecond timer output signal in response to the frequency adjustment signals; and
generating a plurality of output pulse signals that are synchronized with the external reference clock in response to the frequency and phase adjusted nanosecond timer output signal.

10. The timer control method of claim 9 , where acquiring the frequency offset difference comprises receiving input parameters from host software that are stored in one or more control registers.

11. The timer control method of claim 9 , where acquiring the frequency offset difference comprises comparing an external synchronization pulse train signal to the local clock.

12. The timer control method of claim 9 , where generating the plurality of frequency adjustment signals comprises generating a frequency compensation enable signal and nanosecond adjustment signal for adjusting a clock period input to an accumulator at a nanosecond timer core circuitry of the adjustable timer.

13. The timer control method of claim 9 , further comprising continuously monitoring residue frequency offset between the local clock and external reference clock after generating the plurality of frequency adjustment signals to compensate for the frequency offset difference.

14. The timer control method of claim 9 , further comprising:
continuously monitoring the local clock and external reference clock for phase offset differences resulting from timing drift between the local clock and the external reference clock;
generating timing adjustment signals based on the phase offset difference; and
generating a modified frequency and phase adjusted nanosecond timer output signal in response to the timing adjustment signals.

15. The timer control method of claim 14 , where generating timing adjustment signals comprises:
generating a timer offset signal in response to the phase offset difference;
generating a drift tracking enable signal to enable phase adjustment of the frequency and phase adjusted nanosecond timer output signal;
generating a time adjustment enable signal to enable time adjustment; and
generating one or more timer adjustment signals for adjusting the nanosecond timer output signal for timing drift.

16. The timer control method of claim 9 , where generating the plurality of output pulse signals comprises generating an output pulse stream characterized by:
a first parameter specifying if the output pulse stream is a single pulse or periodic pulse;
a second parameter specifying if the output pulse stream is in a reset state;
a third parameter specifying if the output pulse stream is a level signal or pulse signal;
a fourth parameter specifying a pulse width for the output pulse stream; and
a fifth parameter specifying a pulse period for the output pulse stream.

17. The timer control method of claim 9 , where generati

Assignees

• Nxp Usa Inc

Inventors

• Yu Mao

Classifications

• H04J3/0685 Primary

  Clock or time synchronisation in a node; Intranode synchronisation · CPC title

• H04L7/02 Primary

  Speed or phase control by the received code signals, the signals containing no special synchronisation information {(H04L7/0075 takes precedence)} · CPC title

• H04J3/0697

  Synchronisation in a packet node · CPC title

• H04L7/0016

  correction of synchronization errors · CPC title