Deterministic jitter removal using a closed loop digital-analog mechanism

Patent metadata

Field	Value
Publication number	US-9923563-B1
Application number	US-201615389520-A
Country	US
Kind code	B1
Filing date	Dec 23, 2016
Priority date	Dec 23, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference signal to the DPLL via a reference path. A shaper of the reference path can process the analog reference signal and provide a digital signal to a doubler component that doubles the frequency for a digital reference signal. The doubler component itself can add deterministic jitter to the noise of the digital reference signal it provides to the DPLL. An estimation of the DPLL performs various calibration processes to determine the deterministic jitter in the digital domain and provide an analog bias signal to the signal shaper component to correct for the deterministic jitter, keeping it at around zero.

First claim

What is claimed is:

1. An apparatus employed in a mobile device with a digital phase lock loop comprising:
a reference clock component comprising a crystal configured to provide an analog reference signal to a reference path in an analog domain;
a signal shaper component configured to shape the analog reference signal into a square signal, and provide the square signal in a digital domain to a shaper output of the reference path;
a doubler component configured to approximately double the square signal to generate a digital reference signal, and provide the digital reference signal at a doubler output of the reference path to estimate of deterministic jitter based on a local oscillator signal of a local oscillator and the digital reference signal; and
a control loop coupling a digital domain portion of the reference path to an analog domain portion of the reference path with a feedback path to provide an analog bias signal in the analog domain to the shaper, and eliminate the deterministic jitter in the digital domain with the analog bias signal.

2. The apparatus of claim 1 , further comprising:
an estimation component configured to generate an estimation of the deterministic jitter, generate a digital correction based on the estimation, and provide the digital correction to the feedback path to correct a duty cycle at the shaper output of the signal shaper component with the analog bias signal based on the digital correction.

3. The apparatus of claim 2 , wherein the estimation component is further configured to modify the duty cycle of the shaper to be less than about 50% and greater than about 0%, or greater than about 50% and less than about 100% based on the digital correction.

4. The apparatus of claim 2 , wherein the estimation component is further configured to estimate the deterministic jitter at the doubler output based on an integer ambiguity in phase cycles between the digital reference signal and the local oscillator signal, at different frequency levels of the local oscillator.

5. The apparatus of claim 2 , wherein the estimation component is further configured to eliminate a leakage of odd signal harmonics at an antenna port coupled that is coupled to the digital phase lock loop.

6. The apparatus of claim 2 , wherein the estimation component is further configured to generate the digital correction during a boot phase or an initial calibration phase of the digital phase lock loop that is before an operational transmission phase for transmission or reception of wireless signals, and generate an adjustment to the analog bias signal by tracking one or more amplitudes of the deterministic jitter during an operational transmission phase to generate a second digital correction based on the adjustment to keep further estimations of the deterministic jitter at about zero during the transmission or reception.

7. The apparatus of claim 1 , further comprising:
a time to digital converter (TDC) configured to compare phases of the digital reference signal and the local oscillator signal of the local oscillator, at different frequencies of the local oscillator; and
an estimation component configured to determine an amplitude of the deterministic jitter based on a degree of a difference between the phases, and generate the digital correction to the feedback path;
wherein the control loop comprises a digital-to-analog converter configured to generate the analog bias signal based on the digital correction to correct for an integer ambiguity based on the degree of the difference.

8. The apparatus of claim 1 , wherein the doubler component is further configured to generate at least a part of the deterministic jitter at the doubler output.

9. A system for a digital phase locked loop comprising:
a crystal oscillator coupled to a signal shaper component, wherein the signal shaper component is configured to provide a square wave at a shaper output based on an analog signal from the crystal oscillator in an analog domain along an analog portion of a reference signal path;
a doubler component, coupled to the signal shaper component downstream of the reference signal path, configured to provide a digital reference signal to a doubler output in a digital domain along a digital portion of the reference signal path to the DPLL by approximately doubling a square wave frequency of the square wave; and
an estimation component configured to generate an estimation of a deterministic jitter in the digital domain and provide a digital correction that is based on the estimation in the digital domain to a feedback path;
a control loop coupling the feedback path to the digital phase locked loop and to the signal shaper component, configured to provide an analog bias to the signal shaper component in the analog domain based on the digital correction from the estimation of the deterministic jitter in the digital domain, and eliminate the deterministic jitter at the doubler output with the analog bias in the analog domain.

10. The system of claim 9 , wherein a digital-to-analog converter of the control loop is configured to adjust a duty cycle at the shaper output of the signal shaper component and eliminate the deterministic jitter that is estimated in the digital domain by providing the analog bias to the signal shaper component in the analog domain.

11. The system of claim 9 , wherein the estimation component is further configured to generate the estimation of the deterministic jitter based on one or more calibration processes that factor an integer ambiguity in phase measurements of the digital reference signal and of an oscillator signal from an oscillator, and further calibrate the signal shaper component with a voltage bias signal as the analog bias.

12. The system of claim 11 , wherein the estimation component comprises a time-to-digital converter (TDC) configured to perform the one or more calibration processes by comparing phases of the digital reference signal based on the oscillator signal of the oscillator, determining an amplitude of the deterministic jitter based on an offset between the phases of the digital reference signal and a cycle of the oscillator signal, at a plurality of frequencies, and generating the analog bias based on the amplitude of the deterministic jitter.

13. The system of claim 9 , wherein the estimation component is further configured to generate a determination of whether a phase drift between phases of the digital reference signal causes an integer ambiguity relative to an oscillator signal of a voltage controlled oscillator, and estimate the deterministic jitter.

14. The system of claim 13 , wherein the estimation component is further configured to determine a first deterministic jitter estimation of the digital reference signal based on the oscillator signal, and a deterministic jitter estimation of the digital reference signal based on the oscillator signal, at different frequencies of the voltage controlled oscillator.

15. The system of claim 14 , wherein the estimation component is further configured to determine the first deterministic jitter estimation and the second deterministic jitter estimation during a boot phase or a calibration phase of the digital phase locked loop that is before an operational transmission phase for active transmission or reception of wireless signals.

16. The system of claim 15 , wherein the estimation component is further configured to eliminate odd signal harmonic spurs to the digital phase locked loop via the control loop.

17. The system of claim 15 , wherein the estimation component is further configured to generate an adjustment o

Assignees

• Intel Ip Corp

Inventors

• Horovitz Gil
• Banin Elan
• Kushnir Igal
• Farber Aryeh
• Krichman Ran
• Degani Ofir
• Banin Rotem

Classifications

• H03L7/0805

  the loop being adapted to provide an additional control signal for use outside the loop · CPC title

• H03L2207/10

  Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/08 Primary

  Details of the phase-locked loop · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title