Switch turn on in a gate driver circuit

Patent metadata

Field	Value
Publication number	US-11075622-B1
Application number	US-202017112172-A
Country	US
Kind code	B1
Filing date	Dec 4, 2020
Priority date	Sep 10, 2020
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

In one aspect, a gate driver circuit includes a gate driver having a first input connected to a first node and a second input connected to a second node. The gate driver circuit also includes a current source circuit that includes a first transistor and a capacitor having a top plate connected to the source of the first transistor and a bottom plate connected to ground. The gate driver circuit further includes a switch that includes a second transistor. A gate of the second transistor is connected to a drain of the first transistor and a source of the second transistor is connected to the first node.

First claim

What is claimed is:

1. A gate driver circuit comprising:
a gate driver having a first input connected to a first node and a second input connected to a second node;
a current source circuit comprising:
a first transistor; and
a capacitor having a top plate connected to the source of the first transistor and a bottom plate connected to ground; and

a switch, wherein the switch comprises a second transistor, wherein a gate of the second transistor is connected to a drain of the first transistor, and a source of the second transistor is connected to the first node.

2. The gate driver circuit of claim 1 , wherein the current source further comprises a static bias configured to provide a current to the gate of the second transistor.

3. The gate driver circuit of claim 1 , wherein the first transistor is an n-channel metal-oxide-semiconductor field-effect transistor (NMOS).

4. The gate driver circuit of claim 1 , further comprising an epi diode connected to the first node.

5. The gate driver circuit of claim 4 , wherein the gate driver is fabricated in an n-type epitaxial layer.

6. The gate driver circuit of claim 5 , wherein the epi diode comprises the n-type epitaxial layer and a p-type substrate.

7. The gate driver circuit of claim 4 , wherein the capacitor is a first capacitor,
wherein the gate driver circuit is configured to be connected to a second capacitor, wherein the second capacitor has a top plate connected to a drain of the second transistor and a bottom plate connected to the second node,
and, with the switch being open, the epi diode is off in response to a magnitude of negative voltages on the second node not exceeding either (1) a sum of a breakdown voltage of the first clamp and a turn-on voltage of the epi diode, or (2) a sum of a breakdown voltage of the second clamp, the turn-on voltage of the epi diode and a boot voltage of the second capacitor.

8. The gate driver circuit of claim 1 , further comprising a clamp connected to the first node and to the second node.

9. The gate driver circuit of claim 8 , wherein the clamp is a Zener-activated clamp.

10. The gate driver circuit of claim 1 , wherein the switch comprises a clamp connected to the first node and to the top plate of the second capacitor.

11. The gate driver circuit of claim 10 , wherein the switch further comprises a Zener diode having an anode connected to a gate of the second transistor and a cathode connected to the first node.

12. The gate driver circuit of claim 11 , wherein the switch further comprises a resistor having one end connected to the gate of the second transistor and the other end connected to the first node.

13. The gate driver circuit of claim 12 , wherein the second transistor is a p-channel metal-oxide-semiconductor field-effect transistor (PMOS).

14. The gate driver circuit of claim 1 , wherein an output of the gate driver is connected to an external device.

15. The gate driver circuit of claim 14 , wherein the external device is a third transistor.

16. The gate driver circuit of claim 15 , wherein the third transistor is an n-channel metal-oxide-semiconductor field-effect transistor (NMOS),
wherein a gate of the NMOS is connected to the output of the gate driver, and
and a source of the NMOS is connected to the second node.

17. The gate driver circuit of claim 1 , wherein the second node is connected to a load.

18. The gate driver circuit of claim 17 , wherein the load comprises a coil.

19. The gate driver circuit of claim 1 , wherein the circuit is an integrated circuit.

20. The gate driver circuit of claim 1 , the capacitor is a capacitance multiplier.

21. An integrated circuit (IC) comprising:
a gate driver having a first input connected to a first node and a second input connected to a second node;
a current source circuit comprising:
a first transistor;
a capacitor having a top plate connected to the source of the first transistor and a bottom plate connected to ground; and
a static bias configured to provide a current to the gate of a second transistor; and

a switch, wherein the switch comprises the second transistor, wherein a gate of the second transistor is connected to a drain of the first transistor, wherein a source of the second transistor is connected to the first node,
wherein the first transistor is an n-channel metal-oxide-semiconductor field-effect transistor (NMOS),
and the second transistor is a p-channel metal-oxide-semiconductor field-effect transistor (PMOS).

22. The IC of claim 21 , wherein the switch further comprises:
a clamp connected to the first node and to the top plate of the second capacitor;
a Zener diode having an anode connected to the gate of the second transistor and a cathode connected to the first node; and
a resistor having one end connected to the gate of the second transistor and the other end connected to the first node.

23. The IC of claim 22 , wherein the second node is connected to a load, and the load comprises a coil.

Assignees

• Allegro Microsystems Llc

Inventors

• Ross Thomas
• Munroe Michael
• Mcintosh James

Classifications

• H03K17/08122

  in field-effect transistor switches · CPC title

• H03K17/04206 Primary

  in field-effect transistor switches · CPC title