Integrated high side gate driver structure and circuit for driving high side power transistors

Patent metadata

Field	Value
Publication number	US-10096705-B2
Application number	US-201515112830-A
Country	US
Kind code	B2
Filing date	Jan 16, 2015
Priority date	Jan 21, 2014
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

An integrated high side gate driver structure for driving a power transistor. The structure includes a semiconductor substrate having a first polarity semiconductor material in which a first well diffusion including a second polarity semiconductor material is formed. An outer wall of the first well diffusion is abutted to the substrate. A second well diffusion, having first polarity semiconductor material, is arranged inside the first well diffusion such that an outer wall of the second well diffusion abuts an inner wall of the first well diffusion. The structure includes a gate driver having high side positive and negative supply voltage ports, and a driver input and output. The gate driver includes a transistor driver in the second well diffusion such that control and output terminals of the transistor driver are coupled to the driver input and output, respectively. The structure also includes respective electrical connections between the first and second well diffusions and the negative supply voltage port.

First claim

The invention claimed is:

1. A class D amplifier output stage comprising:
an integrated high side gate driver structure for driving a power transistor, including:
a semiconductor substrate comprising a first polarity semiconductor material in which a first well diffusion is formed,
the first well diffusion comprising a second polarity semiconductor material and having a peripheral outer wall abutted to the semiconductor substrate,
a second well diffusion comprising first polarity semiconductor material arranged inside the first well diffusion such that an outer peripheral wall of the second well diffusion is abutted to an inner peripheral wall of the first well diffusion;
a gate driver comprising a high side positive supply voltage port, a high side negative supply voltage port, a driver input and a driver output,
wherein the gate driver comprises a transistor driver arranged in the second well diffusion such that a control terminal and an output terminal of the transistor driver are coupled to the driver input and driver output, respectively, and
a first electrical connection between the first well diffusion and the high side negative supply voltage port and a second electrical connection between the second well diffusion and the high side negative supply voltage port;

the class D amplifier output stage further comprising:
a power transistor comprising a control terminal connected to the driver output of the gate driver, and
a floating voltage regulator arranged in the semiconductor substrate including:
a positive voltage input coupled to a high side DC voltage supply of the class D amplifier output stage,
a regulated DC voltage output coupled to the high side positive supply voltage port of the gate driver, and
a DC voltage reference generator coupled between the high side negative supply voltage port of the gate driver and a reference voltage input of the floating voltage regulator.

2. A class D amplifier output stage according to claim 1 , wherein the outer peripheral wall of the first well diffusion comprises first and second vertical wall sections electrically connected to a horizontal bottom wall section; and
the outer peripheral wall of the second well diffusion comprises first and second vertical wall sections electrically connected to a horizontal bottom wall section.

3. A class D amplifier output stage according to claim 2 , wherein the horizontal bottom wall section of the first well diffusion comprises an N+ polarity or P+ polarity buried layer and the horizontal bottom wall section of the second well diffusion comprises a buried layer of opposite polarity to the buried layer of the first well diffusion.

4. A class D amplifier output stage according to claim 2 , further comprising:
a first transistor body diffusion arranged above the horizontal bottom wall section of the second well diffusion and in abutment to at least one of the first and second vertical wall section(s) of the second well diffusion.

5. A class D amplifier output stage according to claim 4 , wherein the gate driver comprises:
a first MOSFET arranged in the first transistor body diffusion; and
a second MOSFET, of opposite polarity to the first MOSFET, arranged in the first or second vertical wall sections of the second well diffusion.

6. A class D amplifier output stage according to claim 5 , wherein the first MOSFET and the second MOSFET are connected in series between the high side positive and negative supply voltage ports of the gate driver; and
wherein respective drain terminals of the first and second MOSFETs are connected to the driver output.

7. A class D amplifier output stage according to claim 1 , further comprising:
a first well contact arranged in the first well diffusion for establishing the electrical connection to the high side negative supply voltage port; and
a second well contact arranged in the second well diffusion for establishing the electrical connection to the high side negative supply voltage port.

8. A class D amplifier output stage according to claim 1 , further comprising:
a third well diffusion comprising a layer of semiconductor material of the second polarity arranged in the semiconductor substrate adjacent to the first well diffusion,
a second transistor body diffusion comprising a layer of semiconductor material of the first polarity arranged inside the third well diffusion,
a LDMOSFET arranged in the second transistor body diffusion.

9. A class D amplifier output stage according to claim 8 , further comprising electrical wiring electrically connecting a source terminal of the LDMOSFET with the high side positive supply voltage port of the gate driver.

10. A class D amplifier output stage according to claim 1 , wherein the semiconductor substrate comprises a P type epitaxial semiconductor substrate.

11. A class D amplifier output stage according to claim 1 , wherein the floating voltage regulator comprises a pass transistor such as a LDNMOS or LDPMOS transistor, coupled between the positive voltage input and regulated DC voltage output.

12. A class D amplifier output stage according to claim 3 , further comprising:
a first transistor body diffusion arranged above the horizontal bottom wall section of the second well diffusion and in abutment to at least one of the first and second vertical wall section(s) of the second well diffusion.

13. A class D amplifier output stage according to claim 2 , further comprising:
a first well contact arranged in the first well diffusion for establishing the electrical connection to the high side negative supply voltage port; and
a second well contact arranged in the second well diffusion for establishing the electrical connection to the high side negative supply voltage port.

14. A class D amplifier output stage according to claim 3 , further comprising:
a first well contact arranged in the first well diffusion for establishing the electrical connection to the high side negative supply voltage port; and
a second well contact arranged in the second well diffusion for establishing the electrical connection to the high side negative supply voltage port.

15. A class D amplifier output stage according to claim 3 , further comprising:
a first well contact arranged in the first well diffusion for establishing the electrical connection to the high side negative supply voltage port; and
a second well contact arranged in the second well diffusion for establishing the electrical connection to the high side negative supply voltage port.

16. A class D amplifier output stage according to claim 2 , further comprising:
a third well diffusion comprising layers of semiconductor material of a second polarity arranged in the semiconductor substrate adjacent to the first well diffusion,
a second transistor body diffusion comprising a layer of semiconductor material of the first polarity arranged inside the third well diffusion,
a LDMOSFET arranged in the second transistor body diffusion.

17. A class D amplifier output stage according to claim 3 , further comprising:
a third well diffusion comprising layers of semiconductor material of the second polarity arranged in the semiconductor substrate adjacent to the first well diffusion,
a second transistor body diffusion comprising a layer of semiconductor material of the first polarity arranged inside the third well diffusion,
a LDMOSFET arranged in the second transistor body diffusion.

18. A class D amplifier output stage according to claim 4 , further comprising:
a third well diffusion comprising layers of semiconductor mater

Assignees

• Infineon Technologies Austria Ag

Inventors

• Nielsen Allan Nogueras
• Høyerby Mikkel

Classifications

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H01L21/823892

  Electricity · mapped topic

• H03F3/2171

  with field-effect devices (H03F3/2173 - H03F3/2178 take precedence) · CPC title

• H01L29/7816 Primary

  Electricity · mapped topic