Receiver for compensating common mode offset

Patent metadata

Field	Value
Publication number	US-11075610-B2
Application number	US-201916654558-A
Country	US
Kind code	B2
Filing date	Oct 16, 2019
Priority date	Mar 26, 2019
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.

First claim

What is claimed is:

1. A receiver, comprising:
an amplifier configured to receive a transmission signal and generate a first output signal and a second output signal at a first node and a second node by amplifying a first voltage difference between the transmission signal and a reference signal; and
an equalizer connected to the first node and the second node, the equalizer configured to receive the transmission signal and compensate a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.

2. The receiver of claim 1 , wherein the common-mode offset is a third voltage difference between an average voltage level of the first output signal and an average voltage level of the second output signal.

3. The receiver of claim 1 , wherein the equalizer includes:
a first transistor connected to the first node; and
a second transistor connected to the second node, and
the first transistor and the second transistor are configured to adjust a voltage level of the first output signal and a voltage level of the second output signal based on the second voltage difference.

4. The receiver of claim 3 , wherein the amplifier is a first amplifier, and
the equalizer further includes:
a second amplifier configured to generate a third output signal and a fourth output signal by amplifying the first voltage difference between the transmission signal and the reference signal; and
a filtering circuit configured to generate a fifth output signal and a sixth output signal by filtering the third output signal and the fourth output signal.

5. The receiver of claim 4 , wherein a third voltage difference between the fifth output signal and the sixth output signal is determined based on the second voltage difference.

6. The receiver of claim 4 , wherein the first transistor is further configured to adjust the voltage level of the first output signal depending on the fifth output signal, and
the second transistor is further configured to adjust the voltage level of the second output signal depending on the sixth output signal.

7. The receiver of claim 1 , wherein the equalizer is a first equalizer, and
the receiver further includes a second equalizer configured to amplify a third voltage difference between the first output signal and the second output signal.

8. The receiver of claim 1 , wherein the amplifier includes:
a first transistor configured to receive the transmission signal through a gate terminal;
a second transistor configured to receive the reference signal through a gate terminal; and
a source degeneration circuit connected between a source terminal of the first transistor and a source terminal of the second transistor.

9. A receiver comprising:
an amplifier configured to receive a transmission signal and generate a first output signal and a second output signal at a first node and a second node by amplifying a voltage difference between the transmission signal and a reference signal; and
an equalizer connected to the first node and the second node, the equalizer configured to: (i) generate a first feedback signal and a second feedback signal based on the first output signal and the second output signal, respectively, and (ii) compensate a common-mode offset between the first output signal and the second output signal based on the first feedback signal, which is derived by passing the first output signal through a first passive impedance element, and the second feedback signal, which is derived by passing the second output signal through a second passive impedance element;
wherein the equalizer includes:
a first transistor connected to the first node and configured to adjust a voltage level of the first output signal depending on the first feedback signal; and
a second transistor connected to the second node and configured to adjust a voltage level of the second output signal depending on the second feedback signal;
a third transistor and a fourth transistor configured to generate a third output signal and a fourth output signal by amplifying a voltage difference between the first output signal and the second output signal;
a fifth transistor and a sixth transistor configured to generate a fifth output signal and a sixth output signal by amplifying a voltage difference between the third output signal and the fourth output signal; and
a filtering circuit configured to generate the first feedback signal and the second feedback signal, respectively by filtering the fifth output signal and the sixth output signal;
wherein the first passive impedance element is a first resistor; and
wherein the second passive impedance element is a second resistor.

10. A receiver comprising:
an amplifier configured to receive a transmission signal and generate a first output signal and a second output signal at a first node and a second node by amplifying a voltage difference between the transmission signal and a reference signal; and
an equalizer connected to the first node and the second node, the equalizer configured to generate a first feedback signal and a second feedback signal based on the first output signal and the second output signal respectively and compensate a common-mode offset between the first output signal and the second output signal based on the first feedback signal, which has a voltage level determined based on an average voltage level of the first output signal, and the second feedback signal, which has a voltage level determined based on an average voltage level of the second output signal.

11. The receiver of claim 10 , wherein the equalizer further includes:
a filtering circuit configured to generate the first feedback signal and the second feedback signal respectively by filtering the first output signal and the second output signal.

12. The receiver of claim 9 , wherein the equalizer is a first equalizer; and wherein the receiver further includes a second equalizer configured to amplify a voltage difference between the first output signal and the second output signal of the amplifier.

13. A receiver comprising:
a first transistor configured to receive a single-ended signal;
a second transistor configured to receive a reference signal;
a third transistor connected to a first node to which the first transistor is connected; and
a fourth transistor connected to a second node to which the second transistor is connected, wherein
the first transistor and the second transistor are configured to generate a first output signal and a second output signal at the first node and the second node by amplifying a first voltage difference between the single-ended signal and the reference signal, and
the third transistor and the fourth transistor are configured to compensate a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the single-ended signal and the reference signal.

14. The receiver of claim 13 , wherein the common-mode offset is a third voltage difference between an average voltage level of the first output signal and an average voltage level of the second output signal.

15. The receiver of claim 13 , further comprising a fifth transistor and a sixth transistor configured to receive the single-ended signal and the reference signal, respectively, and generate a third output signal and a fourth output signal by amplifying the first voltage difference; and
a filtering circuit configured to generate a fifth output signal and a sixth output signal, respecti

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Seunghwan
• Sung Yoo-Chang
• Kim Wangsoo
• Song Indal

Classifications

• H04L25/0292

  Arrangements specific to the receiver end · CPC title

• H04L25/0274 Primary

  Arrangements for ensuring balanced coupling · CPC title

• H04L25/03006

  Arrangements for removing intersymbol interference · CPC title

• H04B1/16

  Circuits · CPC title

• H03F2200/375

  Circuitry to compensate the offset being present in an amplifier · CPC title