Electronic device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11075439-B2
Application number	US-201916379819-A
Country	US
Kind code	B2
Filing date	Apr 10, 2019
Priority date	Jul 31, 2018
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, a core dielectric layer disposed on the chip package, and an antenna pattern disposed on the core dielectric layer opposite to the chip package. The chip package includes a semiconductor chip, an insulating encapsulation encapsulating the semiconductor chip, and a redistribution structure electrically coupled to the semiconductor chip. The redistribution structure includes a first circuit pattern located at an outermost side of the chip package, and a patterned dielectric layer disposed between the first circuit pattern and the insulating encapsulation. The core dielectric layer is in contact with the first circuit pattern. The core dielectric layer and the patterned dielectric layer are of different materials. The antenna pattern is electrically coupled to the chip package.

First claim

What is claimed is:

1. An electronic device, comprising:
a chip package, comprising:
a semiconductor chip;
an insulating encapsulation, encapsulating the semiconductor chip; and
a redistribution structure, electrically coupled to the semiconductor chip and comprising:
a first circuit pattern, located at an outermost side of the chip package; and
a patterned dielectric layer, disposed between the first circuit pattern and the insulating encapsulation; and

a core dielectric layer, disposed on the chip package, being in contact with the first circuit pattern of the redistribution structure, wherein the core dielectric layer and the patterned dielectric layer of the redistribution structure are of different materials; and
an antenna pattern, disposed on the core dielectric layer opposite to the chip package and electrically coupled to the chip package.

2. The electronic device of claim 1 , wherein the antenna pattern is tapered with first surfaces comprising widths greater than that of second surfaces, the first surfaces opposite to the second surfaces of the antenna pattern are in contact with the core dielectric layer.

3. The electronic device of claim 1 , wherein the first circuit pattern is tapered with third surfaces comprising widths greater than that of fourth surfaces, the third surfaces opposite to the fourth surfaces of the first circuit pattern are connected to the core dielectric layer.

4. The electronic device of claim 1 , further comprising:
a protective layer, disposed on the core dielectric layer and encapsulating the antenna pattern.

5. The electronic device of claim 1 , further comprising:
a patterned mask, covering the antenna pattern, wherein the antenna pattern comprises an undercut.

6. The electronic device of claim 1 , wherein the chip package further comprises:
an attaching layer, disposed between the semiconductor chip and the redistribution structure, comprising a protruding portion embedded in the redistribution structure and in contact with the core dielectric layer.

7. The electronic device of claim 1 , wherein the chip package further comprises:
a conductive element, disposed on the redistribution structure, embedded in the insulating encapsulation, and electrically coupled to the semiconductor chip; and
a conductive joint, connected to the conductive element and the first circuit pattern of the redistribution structure.

8. The electronic device of claim 1 , wherein the chip package further comprises:
a second circuit pattern, disposed on the semiconductor chip and the insulating encapsulation and located opposite to the redistribution structure, wherein a thickness uniformity of the antenna pattern is lower than that of the second circuit pattern of the chip package.

9. The electronic device of claim 1 , wherein the core dielectric layer comprises:
a first sub-layer, connected to at least one of the antenna pattern and the first circuit pattern of the chip package; and
a second sub-layer, connected to the first sub-layer and comprising the adhesion lower than that of the first sub-layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Pei-Hsuan
• Hsieh Ching-Hua
• Hwang Chien-Ling
• Chiu Yu-Ting
• Kuo Jui-Chang

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title