Electronic device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2020044306-A1
Application number	US-201916379819-A
Country	US
Kind code	A1
Filing date	Apr 10, 2019
Priority date	Jul 31, 2018
Publication date	Feb 6, 2020
Grant date	—

Abstract

An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, a core dielectric layer disposed on the chip package, and an antenna pattern disposed on the core dielectric layer opposite to the chip package. The chip package includes a semiconductor chip, an insulating encapsulation encapsulating the semiconductor chip, and a redistribution structure electrically coupled to the semiconductor chip. The redistribution structure includes a first circuit pattern located at an outermost side of the chip package, and a patterned dielectric layer disposed between the first circuit pattern and the insulating encapsulation. The core dielectric layer is in contact with the first circuit pattern. The core dielectric layer and the patterned dielectric layer are of different materials. The antenna pattern is electrically coupled to the chip package.

First claim

What is claimed is:

1 . An electronic device, comprising:
a chip package, comprising:
a semiconductor chip;
an insulating encapsulation, encapsulating the semiconductor chip; and
a redistribution structure, electrically coupled to the semiconductor chip and comprising:
a first circuit pattern, located at an outermost side of the chip package; and
a patterned dielectric layer, disposed between the first circuit pattern and the insulating encapsulation; and

a core dielectric layer, disposed on the chip package, being in contact with the first circuit pattern of the redistribution structure, wherein the core dielectric layer and the patterned dielectric layer of the redistribution structure are of different materials; and an antenna pattern, disposed on the core dielectric layer opposite to the chip package and electrically coupled to the chip package.

2 . The electronic device of claim 1 , wherein the antenna pattern is tapered with first surfaces comprising widths greater than that of second surfaces, the first surfaces opposite to the second surfaces of the antenna pattern are in contact with the core dielectric layer.

3 . The electronic device of claim 1 , wherein the first circuit pattern is tapered with third surfaces comprising widths greater than that of fourth surfaces, the third surfaces opposite to the fourth surfaces of the first circuit pattern are connected to the core dielectric layer.

4 . The electronic device of claim 1 , further comprising:
a protective layer, disposed on the core dielectric layer and encapsulating the antenna pattern.

5 . The electronic device of claim 1 , further comprising:
a patterned mask, covering the antenna pattern, wherein the antenna pattern comprises an undercut.

6 . The electronic device of claim 1 , wherein the chip package further comprises:
an attaching layer, disposed between the semiconductor chip and the redistribution structure, comprising a protruding portion embedded in the redistribution structure and in contact with the core dielectric layer.

7 . The electronic device of claim 1 , wherein the chip package further comprises:
a conductive element, disposed on the redistribution structure, embedded in the insulating encapsulation, and electrically coupled to the semiconductor chip; and a conductive joint, connected to the conductive element and the first circuit pattern of the redistribution structure.

8 . The electronic device of claim 1 , wherein the chip package further comprises:
a second circuit pattern, disposed on the semiconductor chip and the insulating encapsulation and located opposite to the redistribution structure, wherein a thickness uniformity of the antenna pattern is lower than that of the second circuit pattern of the chip package.

9 . The electronic device of claim 1 , wherein the core dielectric layer comprises:
a first sub-layer, connected to at least one of the antenna pattern and the first circuit pattern of the chip package; and a second sub-layer, connected to the first sub-layer and comprising the adhesion lower than that of the first sub-layer.

10 . A method of manufacturing an electronic device, comprising:
providing a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer; and removing at least a portion of each of the two conductive layers to form an antenna pattern and a circuit pattern of a chip package at the two opposite surfaces of the core dielectric layer.

11 . The method of claim 10 , wherein after providing the core dielectric layer with the two conductive layers,
forming a patterned mask to cover one of the two conductive layers, and removing a portion of the one of the two conductive layers exposed by the patterned mask to form the antenna pattern with an undercut.

12 . The method of claim 10 , wherein after providing the core dielectric layer with the two conductive layers,
forming a patterned dielectric layer on one of the two conductive layers, wherein the patterned dielectric layer exposes a portion of the one of the two conductive layers, and removing the portion of the one of the two conductive layers to form the circuit pattern of the chip package, wherein the circuit pattern comprising a slanted sidewall connected to the patterned dielectric layer and the core dielectric layer.

13 . The method of claim 12 , wherein after forming the circuit pattern,
disposing a semiconductor chip with an attaching layer on the patterned dielectric layer opposite to the circuit pattern, wherein a portion of the attaching layer extends to pass through the patterned dielectric layer and the circuit pattern to be in contact with the core dielectric layer.

14 . The method of claim 10 , wherein removing at least the portion of each of the two conductive layers comprises:
removing one of the two conductive layers to expose a surface of the core dielectric layer, and printing a conductive paste on the surface of the core dielectric layer to form the antenna pattern.

15 . The method of claim 10 , further comprising:
thinning one of the two conductive layers before removing at least the portion of each of the two conductive layers.

16 . The method of claim 10 , wherein forming the antenna pattern comprises:
forming a conductive material to cover a portion of the one of the two conductive layers after thinning, and removing a remaining portion of the one of the two conductive layers exposing by the conductive material to form the antenna pattern.

17 . The method of claim 10 , further comprising:
providing an alignment mark on the core dielectric layer before removing at least a portion of each of the two conductive layers, wherein after one of the antenna pattern and the circuit pattern is formed, the alignment mark is employed to remove at least a portion of the other one of the two conductive layers with respect to the core dielectric layer.

18 . A method of manufacturing an electronic device, comprising:
forming a composite structure, wherein the composite structure comprises:
a core dielectric layer, comprising a first surface, a second surface opposite to the first surface, and an alignment mark;
a first conductive layer, formed on the first surface of the core dielectric layer; and
a second conductive layer, formed on the second surface of the core dielectric layer;
patterning the first conductive layer and the second conductive layer to respectively form an antenna pattern and a circuit pattern through the alignment mark; encapsulating the antenna pattern to form an antenna package; encapsulating a plurality of semiconductor chips arranged in form of an array on the circuit pattern to form a chip package, wherein the semiconductor chips are electrically coupled to the circuit pattern and the antenna pattern; and cutting the antenna package, the chip package, and the core dielectric layer disposed therebetween into a plurality of electronic devices.

19 . The method of claim 18 , wherein patterning the first conductive layer comprises:
forming a patterned mask on the first conductive layer, wherein the patterned mask exposes a portion of the first conductive layer, and removing the portion of the first conductive layer to form the antenna pattern with a first undercut.

20 . The method of claim 18 , wherein patterning the second conductive layer comprises:
forming a patterned dielectric layer on the second conductive layer, wherein the patterned dielectric layer exposes a portio

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Pei-Hsuan
• Hsieh Ching-Hua
• Hwang Chien-Ling
• Chiu Yu-Ting
• Kuo Jui-Chang

Classifications

• H01Q1/2283 Primary

  mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package · CPC title

• H01Q1/40 Primary

  Radiating elements coated with or embedded in protective material · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/874

  On different surfaces · CPC title