Thin film transistor, manufacturing method thereof, array substrate and display device

Patent metadata

Field	Value
Publication number	US-11075230-B2
Application number	US-201916596212-A
Country	US
Kind code	B2
Filing date	Oct 8, 2019
Priority date	Oct 12, 2018
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

A thin film transistor, a manufacturing method thereof, an array substrate and a display device are provided. The thin film transistor includes a first electrode on a substrate, a first insulating layer on the first electrode with the first insulating layer having a sidewall, an active layer on the first insulating layer with the active layer connected to the first electrode and comprising a portion on the sidewall which is configured as a channel of the thin film transistor, and a second electrode on the active layer with the second electrode connected to the active layer.

First claim

The invention claimed is:

1. An array substrate comprising a thin film transistor, wherein the array substrate comprises:
a first electrode on a substrate;
a first insulating layer on the first electrode, the first insulating layer having a sidewall;
an active layer on the first insulating layer, wherein the active layer is connected to the first electrode, and wherein a portion of the active layer is on the sidewall of the first insulating layer and is configured as a channel of the thin film transistor; and
a second electrode on the active layer, wherein the second electrode is connected to the active layer,
wherein one of the first electrode and the second electrode is integrated with a pixel electrode of the array substrate, and
wherein another of the first electrode and the second electrode is formed of a same material in a same layer as a data line of the array substrate.

2. The array substrate according to claim 1 ,
wherein the first insulating layer has a groove exposing at least a first portion of the first electrode,
wherein the active layer comprises a U-shaped portion within the groove and a conductive portion outside the groove, and
wherein the U-shaped portion comprises a connection portion at a bottom of the groove and connected to the first electrode, and a channel portion on a sidewall of the groove.

3. The array substrate according to claim 2 , further comprising:
a second insulating layer on the U-shaped portion;
a control electrode on the second insulating layer; and
a third insulating layer on the control electrode, the third insulating layer having a via hole exposing the conductive portion,
wherein the second electrode is on the third insulating layer and is connected to the conductive portion through the via hole.

4. The array substrate according to claim 3 , wherein an orthographic projection of the second insulating layer, an orthographic projection of the control electrode, and an orthographic projection of the U-shaped portion on the substrate coincide with each other.

5. The array substrate according to claim 3 ,
wherein the conductive portion comprises a first conductive portion and a second conductive portion on two sides of the groove,
wherein the via hole in the third insulating layer comprises a first via hole exposing the first conductive portion and a second via hole exposing the second conductive portion, and
wherein the channel portion of the U-shaped portion comprises a first channel portion on a sidewall of the groove close to the first conductive portion, and a second channel portion on a sidewall of the groove close to the second conductive portion.

6. The array substrate according to claim 2 ,
wherein the groove has a shape selected from a group comprising a truncated pyramid, a truncated cone, and a column,
wherein a sectional shape of the groove in a direction parallel to the substrate is selected from a group comprising a square, a rectangle, a circle and an ellipse, and
wherein a sectional shape of the groove in a direction perpendicular to the substrate is selected from a group comprising a trapezoid and a rectangle.

7. The array substrate according to claim 2 ,
wherein the U-shaped portion overlaps all surfaces of the groove, and
wherein the U-shaped portion has an annular three-dimensional structure.

8. The array substrate according to claim 1 ,
wherein the first insulating layer has a protrusion exposing at least a second portion of the first electrode,
wherein the active layer comprises an inverted U-shaped portion on the protrusion and a connection portion on the first electrode, and
wherein the inverted U-shaped portion comprises a conductive portion on a top of the protrusion and a channel portion on a sidewall of the protrusion.

9. The array substrate according to claim 8 , further comprising:
a second insulating layer on the active layer;
a control electrode on the second insulating layer, wherein a position of the control electrode corresponds to a position of the channel portion; and
a third insulating layer on the control electrode, wherein the third insulating layer has a via hole exposing the conductive portion,
wherein the second electrode is on the third insulating layer and is connected to the conductive portion through the via hole.

10. The array substrate according to claim 9 , wherein the channel portion comprises a first channel portion and a second channel portion on two sides of the protrusion.

11. The array substrate according to claim 8 ,
wherein the protrusion has a shape selected from a group comprising a truncated pyramid, a truncated cone, and a column,
wherein a sectional shape of the protrusion in a direction parallel to the substrate is selected from a group comprising a square, a rectangle, a circle and an ellipse, and
wherein a sectional shape of the protrusion in a direction perpendicular to the substrate is selected from a group comprising a trapezoid and a rectangle.

12. The array substrate according to claim 8 ,
wherein the inverted U-shaped portion is on all surfaces of the protrusion, and
wherein the inverted U-shaped portion has an annular three-dimensional structure.

13. The array substrate according to claim 1 ,
wherein the thin film transistor further comprises a control electrode on the active layer,
wherein the control electrode is formed of a same material in a same layer as a gate line of the array substrate.

14. A display device comprising the array substrate according to claim 1 .

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Cao Binbin
• Ye Chengzhi
• Li Fangfang
• An Hui
• Li Hengbin

Classifications

• H10D86/0212

  comprising manufacture, treatment or coating of substrates · CPC title

• H10D30/6758

  characterised by the insulating substrates · CPC title

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title