Display device

Patent metadata

Field	Value
Publication number	US-2016197099-A1
Application number	US-201514976008-A
Country	US
Kind code	A1
Filing date	Dec 21, 2015
Priority date	Jan 6, 2015
Publication date	Jul 7, 2016
Grant date	—

Abstract

A display device includes a substrate, a first insulating layer having a first side wall, an oxide semiconductor layer on the first side wall, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first transparent conductive layer between the oxide semiconductor layer and the substrate, the first transparent conductive layer being connected with a first portion of the oxide semiconductor layer, a first electrode on the first insulating layer on the side opposite to the substrate, the first electrode being connected with a second portion of the oxide semiconductor layer, and a second transparent conductive layer connected with the first transparent conductive layer, the second transparent conductive layer forming the same layer with the first transparent conductive layer.

First claim

What is claimed is:

1 . A display device, comprising:
a substrate; a first insulating layer having a first side wall; an oxide semiconductor layer on the first side wall; a gate electrode facing the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode; a first transparent conductive layer between the oxide semiconductor layer and the substrate, the first transparent conductive layer being connected with a first portion of the oxide semiconductor layer; a first electrode on the first insulating layer on the side opposite to the substrate, the first electrode being connected with a second portion of the oxide semiconductor layer; and a second transparent conductive layer connected with the first transparent conductive layer, the second transparent conductive layer forming the same layer with the first transparent conductive layer.

2 . The display device according to claim 1 , further comprising a second electrode between the substrate and the oxide semiconductor layer, the second electrode being connected with the first portion.

3 . The display device according to claim 2 , further comprising a third transparent conductive layer forming the same layer with the first transparent conductive layer and the second transparent conductive layer, the third transparent conductive layer facing the second transparent conductive layer as seen in a plan view and being electrically separated from the second transparent conductive layer.

4 . The display device according to claim 2 , further comprising:
a fourth transparent conductive layer in a region different from that of at least the second transparent conductive layer as seen in a plan view, the fourth transparent conductive layer being electrically separated from the second transparent conductive layer; and a second insulating layer between the second transparent conductive layer and the fourth transparent conductive layer.

5 . The display device according to claim 4 , further comprising a third insulating layer between the gate electrode and the first electrode;
wherein the second insulating layer includes at least one of the first insulating layer, the gate insulating layer and the third insulating layer.

6 . The display device according to claim 5 , further comprising a third electrode between a top surface of the first insulating layer and the oxide semiconductor layer.

7 . The display device according to claim 6 , wherein the first side wall has a tapered inclining surface tending to close upward.

8 . The display device according to claim 7 , wherein the first side wall is ring-shaped as seen in a plan view.

9 . The display device according to claim 8 , further comprising:
a gate line to be supplied with a gate voltage controlling a transistor including a channel formed of the oxide semiconductor layer to be on or off; and a data line to be supplied with a data signal corresponding to a gray scale of a pixel including the second transparent conductive layer; wherein: the gate line is connected with the gate electrode; the data line is connected with the first electrode; and the transistor includes a crossing area of the gate line and the data line.

10 . The display device according to claim 8 , wherein the first electrode is connected with the oxide semiconductor layer via the third electrode.

11 . A display device, comprising:
a substrate; a first insulating layer having a first side wall; an oxide semiconductor layer on the first side wall; a gate electrode facing the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode; a first transparent conductive layer between the oxide semiconductor layer and the substrate, the first transparent conductive layer being connected with a first portion of the oxide semiconductor layer; a first electrode on the first insulating layer on the side opposite to the substrate, the first electrode being connected with a second portion of the oxide semiconductor layer; and a second transparent conductive layer connected with the first electrode, the second transparent conductive layer forming the same layer with the first transparent conductive layer.

12 . The display device according to claim 11 , further comprising a second electrode between the substrate and the oxide semiconductor layer, the second electrode being connected with the first portion.

13 . The display device according to claim 12 , further comprising a third transparent conductive layer forming the same layer with the first transparent conductive layer and the second transparent conductive layer, the third transparent conductive layer facing the second transparent conductive layer as seen in a plan view and being electrically separated from the second transparent conductive layer.

14 . The display device according to claim 12 , further comprising:
a fourth transparent conductive layer in a region different from that of at least the second transparent conductive layer as seen in a plan view, the fourth transparent conductive layer being electrically separated from the second transparent conductive layer; and a second insulating layer between the second transparent conductive layer and the fourth transparent conductive layer.

15 . The display device according to claim 14 , further comprising a third insulating layer between the gate electrode and the first electrode;
wherein the second insulating layer includes at least one of the first insulating layer, the gate insulating layer and the third insulating layer.

16 . The display device according to claim 15 , further comprising a third electrode between a top surface of the first insulating layer and the oxide semiconductor layer.

17 . The display device according to claim 16 , wherein the first side wall has a tapered inclining surface tending to close upward.

18 . The display device according to claim 17 , wherein the first side wall is ring-shaped as seen in a plan view.

19 . The display device according to claim 18 , further comprising:
a gate line to be supplied with a gate voltage controlling a transistor including a channel formed of the oxide semiconductor layer to be on or off; and a data line to be supplied with a data signal corresponding to a gray scale of a pixel including the second transparent conductive layer; wherein: the gate line is connected with the gate electrode; the data line is connected with the second electrode; and the transistor includes a crossing area of the gate line and the data line.

20 . The display device according to claim 18 , wherein the first electrode is connected with the oxide semiconductor layer via the third electrode.

Assignees

• Japan Display Inc

Inventors

• Sasaki Toshinari

Classifications

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title