Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate

US11075166B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11075166-B2
Application numberUS-202017005002-A
CountryUS
Kind codeB2
Filing dateAug 27, 2020
Priority dateDec 11, 2015
Publication dateJul 27, 2021
Grant dateJul 27, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

First claim

Opening claim text (preview).

What is claimed is: 1. A microelectronic structure, comprising: a first microelectronic device and a second microelectronic device, wherein the first microelectronic device and the second microelectronic device each include a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof; an encapsulant material, wherein a first portion of the encapsulant material is between and in contact with a first side of the first microelectronic device and a first side of the second microelectronic device, a second portion of the encapsulant material is in contact with a second side of the first microelectronic device opposite the first side of the first microelectronic device, and a third portion of the encapsulant material is in contact with a second side of the second microelectronic device opposite the first side of the second microelectronic device; a microelectronic bridge, wherein the microelectronic bridge has a first end attached to the plurality of high density interconnect structures of the first microelectronic device, and the microelectronic bridge has a second end attached to the plurality of high density interconnect structures of the second microelectronic device; and a microelectronic substrate having a cavity defined therein, the cavity extending from a first surface of the microelectronic substrate, wherein the plurality of lower density interconnect structures of the first microelectronic device and the plurality of lower density interconnect structures of the second microelectronic device are electrically attached to the first surface of the microelectronic substrate, and wherein the microelectronic bridge extends into the microelectronic substrate cavity. 2. The microelectronic structure of claim 1 , wherein the microelectronic bridge electrically connects the first microelectronic device to the second microelectronic device. 3. The microelectronic structure of claim 2 , wherein the microelectronic bridge includes a plurality of conductive routes therein. 4. The microelectronic structure of claim 2 , wherein the microelectronic bridge includes at least one microelectronic device embedded therein. 5. A microelectronic structure comprising: a first microelectronic device having an active surface, wherein the first microelectronic device includes a plurality of high density interconnect structures on the active surface thereof and a plurality of lower density interconnect structures on the active surface thereof; a second microelectronic device having an active surface, wherein the second microelectronic device includes a plurality of high density interconnect structures on the active surface thereof and a plurality of lower density interconnect structures on the active surface thereof; a microelectronic bridge having a first end attached to the plurality of high density interconnect structures of the first microelectronic device, and the microelectronic bridge having a second end attached to the plurality of high density interconnect structures of the second microelectronic device; a microelectronic substrate having a cavity defined therein, the cavity extending from a first surface of the microelectronic substrate, wherein the plurality of lower density interconnect structures of the first microelectronic device and the plurality of lower density interconnect structures of the second microelectronic device are electrically attached to the first surface of the microelectronic substrate, and wherein the microelectronic bridge extends into the microelectronic substrate cavity; an adhesive layer between and in contact with a bottom of the microelectronic bridge and a bottom of the cavity; and an underfill material between the first microelectronic device active surface and the microelectronic substrate first surface, between the second microelectronic device active surface and the microelectronic substrate first surface, and within a portion of the microelectronic substrate cavity, the underfill material in contact with the adhesive layer. 6. The microelectronic structure of claim 5 , further comprising: an encapsulant material, wherein a first portion of the encapsulant material is between and in contact with a first side of the first microelectronic device and a first side of the second microelectronic device, a second portion of the encapsulant material is in contact with a second side of the first microelectronic device opposite the first side of the first microelectronic device, and a third portion of the encapsulant material is in contact with a second side of the second microelectronic device opposite the first side of the second microelectronic device. 7. The microelectronic structure of claim 5 , wherein the microelectronic bridge electrically connects the first microelectronic device and the second microelectronic device. 8. The microelectronic structure of claim 7 , wherein the microelectronic bridge includes a plurality of conductive routes therein. 9. The microelectronic structure of claim 7 , wherein the microelectronic bridge includes at least one microelectronic device embedded therein. 10. A computing device, comprising: a board; and a microelectronic structure attached to the board, wherein the microelectronic structure comprises: a first microelectronic device and a second microelectronic device, wherein the first microelectronic device and the second microelectronic device each include a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof; an encapsulant material, wherein a first portion of the encapsulant material is between and in contact with a first side of the first microelectronic device and a first side of the second microelectronic device, a second portion of the encapsulant material is in contact with a second side of the first microelectronic device opposite the first side of the first microelectronic device, and a third portion of the encapsulant material is in contact with a second side of the second microelectronic device opposite the first side of the second microelectronic device; a microelectronic bridge, wherein the microelectronic bridge has a first end attached to the plurality of high density interconnect structures of the first microelectronic device, and the microelectronic bridge has a second end attached to the plurality of high density interconnect structures of the second microelectronic device; and a microelectronic substrate having a cavity defined therein, the cavity extending from a first surface of the microelectronic substrate, wherein the plurality of lower density interconnect structures of the first microelectronic device and the plurality of lower density interconnect structures of the second microelectronic device are electrically attached to the first surface of the microelectronic substrate, and wherein the microelectronic bridge extends into the microelectronic substrate cavity. 11. The computing device of claim 10 , wherein the microelectronic bridge electrically connects the first microelectronic device to the second microelectronic device. 12. The computing device of claim 11 , wherein the microelectronic bridge includes a plurality of conductive routes therein. 13. The computing device of claim 11 , wherein the microelectronic bridge includes at least one microelectronic device embedded therein. 14. A computing device, comprising: a board; and a microelectronic structure attached to the board, wherein the microelectronic structure comprises: a first microelectronic device having an active surface, wherei

Assignees

Inventors

Classifications

  • Materials of bond wires · CPC title

  • the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

  • the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

  • comprising holes having chips therein · CPC title

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What does patent US11075166B2 cover?
A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attache…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W70/68. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 27 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).