Wafer scale ultrasonic sensing device and manufacturing method thereof

US11075072B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11075072-B2
Application numberUS-202016874244-A
CountryUS
Kind codeB2
Filing dateMay 14, 2020
Priority dateJul 12, 2019
Publication dateJul 27, 2021
Grant dateJul 27, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A wafer scale ultrasonic sensing device includes a substrate assembly, an ultrasonic component, a first protective layer, a first conductive circuit, a second conductive circuit, a second protective layer, a conductive material, electrical connection layers, and soldering portions. The substrate assembly includes a first wafer and a second wafer, and the second wafer covers a groove on the first wafer to define a hollow chamber. The first wafer, the second wafer, and the first protective layer are coplanar with the first conductive circuit on a first side surface and coplanar with the second conductive circuit on a second side surface. The second protective layer has an opening, where the conductive material is in the opening and is in contact with the ultrasonic component. The electrical connection layers are on the first side surface and the second side surface, and the soldering portions are respectively connected to the electrical connection layers.

First claim

Opening claim text (preview).

What is claimed is: 1. A wafer scale ultrasonic sensing device, comprising: a substrate assembly, comprising a first wafer and a second wafer, wherein the first wafer is provided with a groove, and the second wafer is bonded with the first wafer and covers the groove to define a hollow chamber; an ultrasonic component on the second wafer, wherein projections of the ultrasonic component and the hollow chamber are overlapped in a perpendicular direction; a first protective layer on a first surface of the second wafer and surrounding the ultrasonic component; a first conductive circuit and a second conductive circuit on the first protective layer, and connected to an upper surface of the ultrasonic component, wherein the first wafer, the second wafer, the first protective layer and the first conductive circuit are coplanar on a first side surface, and the first wafer, the second wafer, the first protective layer and the second conductive circuit are coplanar on a second side surface; a second protective layer covering the first conductive circuit and the second conductive circuit, wherein the second protective layer has an opening, and the upper surface of the ultrasonic component corresponds to the opening; a conductive material within the opening and in contact with the upper surface of the ultrasonic component; two electrical connection layers on the first side surface and the second side surface respectively, and connected to the first conductive circuit and the second conductive circuit; and two soldering portions on a bottom surface of the first wafer, and connected to the two electrical connection layers respectively. 2. The wafer scale ultrasonic sensing device according to claim 1 , wherein the ultrasonic component comprises a first piezoelectric layer, a first electrode, a second piezoelectric layer and a second electrode that are sequentially stacked on the second wafer, the second piezoelectric layer and the second electrode do not cover a part of an upper surface of the first electrode, the conductive material is in contact with the second electrode, and the first electrode and the second electrode are respectively connected to the first conductive circuit and the second conductive circuit. 3. The wafer scale ultrasonic sensing device according to claim 1 , wherein the ultrasonic component comprises a first ultrasonic unit and a second ultrasonic unit, the first ultrasonic unit comprises a first piezoelectric layer and a first electrode, the first piezoelectric layer is on the second wafer, the first piezoelectric layer and the first protective layer are provided with a first contact hole for communication, the first electrode is covered in the first piezoelectric layer, a part of the first electrode is exposed in the first contact hole, and a part of the first conductive circuit is in the first contact hole and is connected to the first electrode; the second ultrasonic unit is not overlapped with the first ultrasonic unit in a direction perpendicular to the second wafer, the second ultrasonic unit comprises a second piezoelectric layer, a second circuit pattern layer and a second electrode, the second piezoelectric layer is on the second wafer, the second piezoelectric layer and the first piezoelectric layer are in a same layer and separated from each other, the second circuit pattern layer is covered in the second piezoelectric, the second circuit pattern layer and the first electrode are in a same layer and separated from each other, the second electrode is on the second piezoelectric layer, the first protective layer is provided with a second contact hole, the second contact hole is in communication with the opening, a part of the second conductive circuit is in the second contact hole and is connected to the second electrode, and a part of the conductive material is filled in the second contact hole and is in contact with the second electrode. 4. The wafer scale ultrasonic sensing device according to claim 1 , wherein the conductive material is polydimethylsiloxane. 5. A manufacturing method of a wafer scale ultrasonic sensing device, comprising: a substrate preparation step: providing a first wafer and a composite substrate, wherein the first wafer is provided with a groove, and the composite substrate comprises a second wafer, an insulating layer and a third wafer that are sequentially stacked; a bonding step: anodic bonding the second wafer with the first wafer, wherein the second wafer covers the groove, so that the groove forms a hollow chamber; a removing step: removing the insulating layer and the third wafer on the insulating layer to complete a substrate assembly; an ultrasonic component forming step: forming an ultrasonic component on the second wafer, wherein projections of the ultrasonic component and the hollow chamber are overlapped in a perpendicular direction, and the ultrasonic component comprises a first electrode and a second electrode that is not electrically connected to the first electrode; a first protective layer forming step: forming a first protective layer on an upper surface of the ultrasonic component and a first surface of the second wafer, wherein the first protective layer is provided with a first contact hole and a second contact hole, and a part of the first electrode and a part of the second electrode are exposed in the first contact hole and the second contact hole respectively; a circuit connecting step: forming a first conductive circuit and a second conductive circuit on the first protective layer, wherein a part of the first conductive circuit and a part of the second conductive circuit are in the first contact hole and the second contact hole respectively, and are connected to the first electrode and the second electrode of the ultrasonic component respectively; a second protective layer forming step: forming a second protective layer to cover the first conductive circuit and the second conductive circuit; an opening forming step: forming an opening on the second protective layer, wherein at least a part of the second electrode is exposed in the opening; a removing step: removing a part of the substrate assembly, a part of the first protective layer, a part of the first conductive circuit, and a part of the second conductive circuit to form a first side surface on which the first wafer, the second wafer, the first protective layer and the first conductive circuit are coplanar, and a second side surface on which the first wafer, the second wafer, the first protective layer and the second conductive circuit are coplanar; an electrical connection layer forming step: forming electrical connection layers on the first side surface and the second side surface respectively, wherein the electrical connection layers are connected to the first conductive circuit and the second conductive circuit respectively; a soldering portion forming step: forming two soldering portions on a surface of the first wafer, wherein the soldering portions are respectively connected to the electrical connection layers; and a conductive material filling step: filling a conductive material in the opening, wherein the conductive material is in contact with the upper surface of the ultrasonic component. 6. The manufacturing method of a wafer scale ultrasonic sensing device according to claim 5 , further comprising a grinding step before the bonding step, wherein a thickness of the second wafer is reduced in the grinding step. 7. The manufacturing method of a wafer scale ultrasonic sensing device according to claim 5 , further comprising: a carrier plate covering step after the opening forming step, wherein the carrier plate covering step comprises covering a carrier plate on the second protective layer to shield the opening; and a carrier plate removi

Assignees

Inventors

Classifications

  • Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • Techniques · CPC title

  • batch processes · CPC title

  • H10P90/123Primary

    by grinding or lapping · CPC title

  • non-optical, e.g. ultrasonic or capacitive sensing · CPC title

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Frequently asked questions

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What does patent US11075072B2 cover?
A wafer scale ultrasonic sensing device includes a substrate assembly, an ultrasonic component, a first protective layer, a first conductive circuit, a second conductive circuit, a second protective layer, a conductive material, electrical connection layers, and soldering portions. The substrate assembly includes a first wafer and a second wafer, and the second wafer covers a groove on the firs…
Who is the assignee on this patent?
J Metrics Tech Co Ltd, Univ Peking Shenzhen Graduate School
What technology area does this patent fall under?
Primary CPC classification H10P90/123. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 27 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).