Class AB buffer with multiple output stages

Patent metadata

Field	Value
Publication number	US-11070180-B2
Application number	US-201916395334-A
Country	US
Kind code	B2
Filing date	Apr 26, 2019
Priority date	Apr 26, 2019
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.

First claim

What is claimed is:

1. A class AB buffer, comprising:
an output stage, comprising:
a first output transistor;
a second output transistor coupled to the first output transistor; and

an input stage coupled to the output stage, and comprising:
a first cascode transistor;
a first switch coupled to the first cascode transistor and the first output transistor;
a second cascode transistor;
a second switch coupled to the first switch, the second cascode transistor, and the first output transistor;
a third cascode transistor;
a third switch coupled to the third cascode transistor and the second output transistor;
a fourth cascode transistor; and
a fourth switch coupled to the third switch, the fourth cascode transistor, and the second output transistor.

2. The class AB buffer of claim 1 , wherein:
the first output transistor, the first switch and the third switch are positive metal oxide semiconductor (PMOS) transistors; and
the second output transistor, the second switch, and the fourth switch are negative metal oxide semiconductor (NMOS) transistors.

3. A class AB buffer, comprising:
a first output stage, comprising:
a first output transistor;
a second output transistor coupled to the first output transistor;

an input stage coupled to the first output stage, and comprising:
a first cascode transistor;
a first switch coupled to the first cascode transistor and the first output transistor;
a second cascode transistor; and
a second switch coupled to the first switch, the second cascode transistor, and the first output transistor; and

a second output stage comprising:
a third output transistor; and
a fourth output transistor coupled to the third output transistor; and

the input stage further comprises:
a third switch coupled to the first cascode transistor and the third output transistor; and
a fourth switch coupled to the third switch, the second cascode transistor, and the third output transistor.

4. The class AB buffer of claim 3 , further comprising:
a fifth switch coupled to the third output transistor and a first power rail; and
a sixth switch coupled to the fourth output transistor and a second power rail.

5. The class AB buffer of claim 3 , wherein the input stage further comprises:
a third cascode transistor;
a fifth switch coupled to the third cascode transistor and the fourth output transistor;
a fourth cascode transistor; and
a sixth switch coupled to the fifth switch, the fourth cascode transistor, and the fourth output transistor.

6. The class AB buffer of claim 5 , wherein:
the third output transistor, the third switch, and the fifth switch are PMOS transistors; and
the fourth output transistor, the fourth switch, and the sixth switch are NMOS transistors.

7. The class AB buffer of claim 1 , further comprising:
a fifth switch coupled to the first output transistor and a first power rail; and
a sixth switch coupled to the second output transistor and a second power rail.

8. A class AB buffer, comprising:
a first output stage, comprising a first positive metal oxide semiconductor (PMOS) output transistor;
an input stage comprising:
a PMOS cascode transistor;
a first PMOS switch comprising a source terminal coupled to a drain terminal of the PMOS cascode transistor;
a first negative metal oxide semiconductor (NMOS) switch comprising a drain terminal coupled to a drain terminal of the first PMOS switch and a gate terminal of the first PMOS output transistor; and
an NMOS cascode transistor comprising a drain terminal coupled to a source terminal of the first NMOS switch;

a second output stage comprising a second PMOS output transistor; and
wherein the input stage further comprises:
a second PMOS switch comprising a source terminal coupled to the drain terminal of the PMOS cascode transistor;
a second NMOS switch comprising:
a drain terminal coupled to a drain terminal of the second PMOS switch and a gate terminal of the second PMOS output transistor; and
a source terminal coupled to the drain terminal of the NMOS cascode transistor.

9. The class AB buffer of claim 8 , further comprising an enable switch comprising:
a first terminal coupled to the gate terminal of the second PMOS output transistor; and
a second terminal coupled to a power rail.

10. The class AB buffer of claim 8 , wherein:
the PMOS cascode transistor is a first PMOS cascode transistor;
the NMOS cascode transistor is a first NMOS cascode transistor;
the second output stage further comprises a first NMOS output transistor comprising a drain terminal coupled to a drain terminal of the second PMOS output transistor; and
the input stage further comprises:
a second PMOS cascode transistor comprising a source terminal coupled to a source terminal of the first PMOS cascode transistor;
a third PMOS switch comprising a source terminal coupled to a drain terminal of the second PMOS cascode transistor;
a third NMOS switch comprising a drain terminal coupled to a drain terminal of the third PMOS switch and a gate terminal of the first NMOS output transistor; and
a second NMOS cascode transistor comprising a drain terminal coupled to a source terminal of the third NMOS switch.

11. The class AB buffer of claim 10 , further comprising an enable switch comprising:
a first terminal coupled to the gate terminal of the first NMOS output transistor; and
a second terminal coupled to a power rail.

12. The class AB buffer of claim 10 , wherein:
the first output stage further comprises a second NMOS output transistor comprising a drain terminal coupled to a drain terminal of the first PMOS output transistor; and
the input stage further comprises:
a fourth PMOS switch comprising a source terminal coupled to the drain terminal of the second PMOS cascode transistor;
a fourth NMOS switch comprising:
a drain terminal coupled to a drain terminal of the fourth PMOS switch and a gate terminal of the second NMOS output transistor; and
a source terminal coupled to the drain terminal of the second NMOS cascode transistor.

13. The class AB buffer of claim 12 , further comprising an enable switch comprising:
a first terminal coupled to the gate terminal of the second NMOS output transistor; and
a second terminal coupled to a power rail.

14. The class AB buffer of claim 8 , further comprising an enable switch comprising:
a first terminal coupled to the gate terminal of the first PMOS output transistor; and
a second terminal coupled to a power rail.

15. A class AB buffer, comprising:
a first output stage, comprising:
a first positive metal oxide semiconductor (PMOS) output transistor; and
a first negative metal oxide semiconductor (NMOS) output transistor comprising a drain terminal coupled to a drain terminal of the first PMOS output transistor;

a second output stage, comprising:
a second PMOS output transistor; and
a second NMOS output transistor comprising a drain terminal coupled to a drain terminal of the second PMOS output transistor; and

an input stage comprising:
a first PMOS cascode transistor;
a second PMOS cascode transistor comprising a source terminal coupled to a source terminal of the first PMOS cascode transistor;
a first NMOS cascode transistor;
a second NMOS cascode transistor comprising a source terminal coupled to a source terminal of the first NMOS cascode transistor;
a first PMOS switch comprising:
a source terminal coupled to a drain terminal of the first PMOS cascode transistor; and
a drain terminal coupled to a gate terminal of the first PMOS output transistor;

a second PMOS switch comprising:
a source

Assignees

• Texas Instruments Inc

Inventors

• Agarwal Nitin
• Roy Aniruddha

Classifications

• H03F3/45188

  Non-folded cascode stages · CPC title

• H03F3/45192

  Folded cascode stages · CPC title

• H03F2200/129

  there being a feedback over the complete amplifier · CPC title

• H03F2203/45352

  the AAC comprising a combination of a plurality of transistors, e.g. Darlington coupled transistors · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title