Operational amplifier, integrated circuit, and method for operating the same

Patent metadata

Field	Value
Publication number	US-11353909-B2
Application number	US-202016832914-A
Country	US
Kind code	B2
Filing date	Mar 27, 2020
Priority date	Mar 27, 2020
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

An operational amplifier comprises a front stage and an output stage. The front stage comprises a first input transistor, a second input transistor, a first node, a second node, and a first current mirror. A first voltage based on a first current through the first input transistor is generated on the first node. A second voltage based on a second current through the second input transistor is generated on the second node. The output stage is configured to output an output voltage based on at least one of the first voltage and the second voltage. The first current mirror comprises a first transistor having a drain connected to the first node, a second transistor having a drain connected to the second node, and a first offset canceling capacitor connected between gates of the first transistor and the second transistor.

First claim

What is claimed is:

1. An operational amplifier, comprising:
a front stage comprising:
a first input transistor;
a second input transistor;
a first node on which a first voltage is generated depending on a first current through the first input transistor;
a second node on which a second voltage is generated depending on a second current through the second input transistor; and
a first current mirror; and

an output stage configured to generate an output voltage depending on at least one of the first voltage and the second voltage;
wherein the first current mirror comprises:
a first transistor having a drain connected to the first node;
a second transistor having a drain connected to the second node; and
a first offset canceling capacitor connected between gates of the first transistor and the second transistor, and

wherein the front stage is configured to program the first offset canceling capacitor with a voltage generated between the first node and the second node.

2. The operational amplifier of claim 1 , wherein the front stage further comprises a first calibration enable switch connected in series to the first offset canceling capacitor between the first node and the second node.

3. An operational amplifier, comprising:
a front stage comprising:
a first input transistor,
a second input transistor,
a first node on which a first voltage is generated depending on a first current through the first input transistor,
a second node on which a second voltage is generated depending on a second current through the second input transistor, and
a first current mirror; and

an output stage configured to generate an output voltage depending on at least one of the first voltage and the second voltage,
wherein the first current mirror comprises:
a first transistor having a drain connected to the first node,
a second transistor having a drain connected to the second node, and
a first offset canceling capacitor connected between gates of the first transistor and the second transistor,

wherein an input terminal of the operational amplifier is connected to a gate of one of the first input transistor and the second input transistor, and
wherein the front stage is further configured to connect an output terminal of the operational amplifier to a gate of the other of the first input transistor and the second input transistor.

4. The operational amplifier of claim 3 , wherein the front stage is configured to short-circuit the gates of the first input transistor and the second input transistor.

5. The operational amplifier of claim 1 , further comprising switch circuitry configured to selectively connect the output stage to the front stage.

6. An operational amplifier, comprising:
a front stage comprising:
a first input transistor,
a second input transistor,
a first node on which a first voltage is generated depending on a first current through the first input transistor,
a second node on which a second voltage is generated depending on a second current through the second input transistor, and
a first current mirror;

an output stage configured to generate an output voltage depending on at least one of the first voltage and the second voltage; and
switch circuitry configured to selectively connect the output stage to the front stage,
wherein the first current mirror comprises:
a first transistor having a drain connected to the first node,
a second transistor having a drain connected to the second node, and
a first offset canceling capacitor connected between gates of the first transistor and the second transistor,

wherein the operational amplifier has a calibration state in which the operational amplifier is calibrated,
wherein an input terminal of the operational amplifier is connected to a gate of the first input transistor,
wherein an output terminal of the operational amplifier is connectable to a gate of the second input transistor,
wherein, in the calibration state, the front stage is configured to:
short-circuit the gates of the first input transistor and the second input transistor,
disconnect the gate of the second input transistor from the output terminal, and
connect the first offset canceling capacitor between the first node and the second node, and

wherein the switch circuitry is configured to disconnect the output stage from the front stage in the calibration state.

7. The operational amplifier of claim 6 , wherein the operational amplifier further has an operation state,
wherein, in the operation state, the front stage is configured to:
disconnect the gate of the first input transistor from the gate of the second input transistor;
connect the gate of the second input transistor to the output terminal; and
disconnect the first offset canceling capacitor from one of the first node and the second node,
wherein the switch circuitry is configured to connect the output stage to the front stage in the operation state.

8. The operational amplifier of claim 1 , wherein the first current mirror further comprises a first gate-biased transistor connected between the output stage and the first transistor, the first gate-biased transistor having a gate biased with a first fixed bias voltage.

9. An operational amplifier, comprising:
a front stage comprising:
a first input transistor,
a second input transistor,
a first node on which a first voltage is generated depending on a first current through the first input transistor,
a second node on which a second voltage is generated depending on a second current through the second input transistor, and
a first current mirror; and

an output stage configured to generate an output voltage depending on at least one of the first voltage and the second voltage,
wherein the first current mirror comprises:
a first transistor having a drain connected to the first node,
a second transistor having a drain connected to the second node, and
a first offset canceling capacitor connected between gates of the first transistor and the second transistor,

wherein the front stage further comprises:
a third input transistor,
a fourth input transistor,
a third node on which a third voltage is generated depending on a third current through the third input transistor,
a fourth node on which a fourth voltage is generated depending on a fourth current through the fourth input transistor, and

a second current mirror comprises:
a third transistor having a drain connected to the third node,
a fourth transistor having a drain connected to the fourth node, and
a second offset canceling capacitor connected between gates of the third transistor and the fourth transistor.

10. The operational amplifier of claim 9 , wherein the front stage is configured to program the second offset canceling capacitor with a voltage generated between the third node and the fourth node.

11. The operational amplifier of claim 10 , wherein the front stage further comprises:
a first gate-biased transistor connected between the output stage and the first current mirror, the first gate-biased transistor having a gate biased with a first fixed bias voltage, and
a second gate-biased transistor connected between the output stage and the first current mirror, the first gate-biased transistor having a gate biased with a second fixed bias voltage.

12. An integrated circuit, comprising:
an operational amplifier; and
input voltage supply circuitry configured to supply an input voltage to the operational amplifier,
wherein the operational amplifier comprises:
a front stage comprising:
a first input transistor,
a second input transistor,
a first node on which a first voltage is generated de

Assignees

• Synaptics Inc

Inventors

• Saeki Yutaka

Classifications

• G05F3/26 Primary

  Current mirrors · CPC title

• H03F3/45192

  Folded cascode stages · CPC title

• H03F3/45753

  using switching means, e.g. sample and hold · CPC title

• H03F2203/30081

  the pull transistor circuit comprising one or more capacitors · CPC title

• H03F2203/30114

  the push transistor circuit comprising one or more capacitors · CPC title