Detector circuit and wireless communication apparatus

Patent metadata

Field	Value
Publication number	US-10348285-B2
Application number	US-201816106566-A
Country	US
Kind code	B2
Filing date	Aug 21, 2018
Priority date	Aug 23, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

A detector circuit includes a first inverter including an input node coupled via a first capacitor to a transmission path for transmitting an AC signal, the first inverter outputting an output voltage in accordance with power of the AC signal, wherein the output voltage increases with increasing temperature, a second inverter including an input node coupled to the transmission path, the second inverter outputting an output voltage in accordance with power of the AC signal, wherein the output voltage decreases with increasing temperature, a third capacitor including one electrode coupled to either an output electrode of the first inverter or an output node of the second inverter, a first resistor coupled between the output node of the first inverter and an output node of the detector circuit, and a second resistor coupled between the output node of the second inverter and the output node of the detector circuit.

First claim

What is claimed is:

1. A detector circuit comprising:
a first inverter including an input node coupled via a first capacitor to a transmission path for transmitting an AC signal, the first inverter outputting an output voltage in accordance with power of the AC signal, wherein the output voltage increases with increasing temperature;
a second inverter including an input node coupled via a second capacitor to the transmission path, the second inverter outputting an output voltage in accordance with power of the AC signal, wherein the output voltage decreases with increasing temperature;
a third capacitor including one electrode coupled to either an output electrode of the first inverter or an output node of the second inverter;
a first resistor coupled between the output node of the first inverter and an output node of the detector circuit; and
a second resistor coupled between the output node of the second inverter and the output node of the detector circuit.

2. The detector circuit according to claim 1 ,
wherein the first resistor and the second resistor have resistances in accordance with a ratio between a variation in the output voltage of the first inverter and a variation in the output voltage of the second inverter relative to temperature change, respectively.

3. The detector circuit according to claim 1 ,
wherein the first inverter includes a first P-channel transistor and a first N-channel transistor having a saturation current value smaller than a saturation current value of the first P-channel transistor, and
wherein the second inverter includes a second P-channel transistor and a second N-channel transistor having a saturation current value greater than a saturation current value of the second P-channel transistor.

4. The detector circuit according to claim 1 ,
wherein the input node of the first inverter and the input node of the second inverter are respectively biased to predetermined voltages.

5. The detector circuit according to claim 1 , further comprising
bias circuits that respectively bias the input node of the first inverter and the input node of the second inverter to predetermined voltages.

6. A wireless communication apparatus comprising:
a power amplifier that amplifies power of an AC signal to be transmitted;
an antenna that transmits the AC signal input by the power amplifier; and
a detector circuit that detects power of the AC signal,
wherein the detector circuit includes
a first inverter that outputs an output voltage in accordance with power of the AC signal input via a first capacitor, the output voltage increasing with increasing temperature,
a second inverter that outputs an output voltage in accordance with power of the AC signal input via a second capacitor, the output voltage decreasing with increasing temperature,
a third capacitor including one electrode coupled to either an output node of the first inverter or an output node of the second inverter,
a first resistor coupled between the output node of the first inverter and an output node of the detector circuit, and
a second resistor coupled between the output node of the second inverter and the output node of the detector circuit.

7. The wireless communication apparatus according to claim 6 , wherein the detector circuit is coupled between the power amplifier and the antenna.

8. A wireless communication apparatus comprising:
an antenna;
an amplifier that amplifies an AC signal received by the antenna;
a demodulation circuit that detects the AC signal amplified by the amplifier;
a converter that converts the demodulated AC signal to a digital signal; and
a detector circuit that that detects power of the AC signal,
wherein the detector circuit includes
a first inverter that outputs an output voltage in accordance with power of the AC signal input via a first capacitor, the output voltage increasing with increasing temperature,
a second inverter that outputs an output voltage in accordance with power of the AC signal input via a second capacitor, the output voltage decreasing with increasing temperature,
a third capacitor including one electrode coupled to an output node of either an output node of the first inverter or an output node of the second inverter,
a first resistor coupled between the output node of the first inverter and an output node of the detector circuit, and
a second resistor coupled between an output node of the second inverter and the output node of the detector circuit.

9. The wireless communication apparatus according to claim 8 , wherein the detector circuit is coupled between the amplifier and the demodulation circuit.

10. The wireless communication apparatus according to claim 8 , wherein the detector circuit is coupled between the demodulation circuit and the converter.

Assignees

• Fujitsu Ltd

Inventors

• Soga Ikuo

Classifications

• H03F3/19

  with semiconductor devices only · CPC title

• H03K5/26 Primary

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• H03K5/2481

  with at least one differential stage · CPC title

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03K5/082

  with an adaptive threshold · CPC title