Semiconductor wafer, bonding structure and wafer bonding method

Patent metadata

Field	Value
Publication number	US-11069647-B2
Application number	US-201916598898-A
Country	US
Kind code	B2
Filing date	Oct 10, 2019
Priority date	Apr 22, 2019
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A semiconductor wafer, a bonding structure, and a wafer bonding method are provided. In the semiconductor wafer, a bonding pad which is electrically connected to the interconnection structure is formed in the top cover layer, and a bonding alignment mark formed by a point array is disposed in the top cover layer. In this way, the bonding alignment mark is disposed in the top cover layer, and the top cover layer is not covered by another material layer, thereby facilitating recognition of the alignment pattern by the bonding device and increasing the alignment window in bonding process. Moreover, the bonding alignment mark is formed by a point array, thereby facilitating integration of the process for forming the bonding alignment mark with the bonding hole process and avoiding defects such as the dishing phenomenon in the manufacturing process.

First claim

The invention claimed is:

1. A semiconductor wafer, comprising:
a semiconductor substrate;
a device structure on the semiconductor substrate, and an interconnection structure for the device structure;
a top cover layer covering the interconnection structure;
a bonding pad disposed in the top cover layer, wherein the bonding pad is arranged in contact with and is connected to the interconnection structure; and
a bonding alignment mark disposed in the top cover layer;
wherein a pattern of the bonding alignment mark comprises a plurality of sub-patterns, each of the plurality of sub-patterns comprises an array of dots, and a smallest distance among the plurality of sub-patterns is greater than a distance between centers of adjacent dots in the array of one of the plurality of sub-patterns.

2. The semiconductor wafer according to claim 1 , wherein the pattern of the bonding alignment mark is centrally symmetric.

3. The semiconductor wafer according to claim 2 , wherein the plurality of sub-patterns comprise sub-patterns which form a surrounding pattern, and sub-patterns which form a central pattern, and the central pattern is surrounded by the surrounding pattern.

4. The semiconductor wafer according to claim 3 , wherein the surrounding pattern includes a sub-pattern having a polygonal shape.

5. The semiconductor wafer according to claim 3 , wherein the surrounding pattern has a polygonal shape, and the sub-patterns forming surrounding pattern have a strip shape.

6. The semiconductor wafer according to claim 2 , wherein the pattern of the bonding alignment mark comprises multiple regions, and sub-patterns in adjacent regions extend in different directions.

7. The semiconductor wafer according to claim 1 , wherein the semiconductor wafer comprises chip regions arranged in an array, the device structure is located the chip regions, and the bonding alignment mark is located in scribe lines between adjacent chip regions.

8. The semiconductor wafer according to claim 1 , wherein each dot in the array corresponds to a circular cylinder, an elliptical cylinder or a rectangular cylinder that is disposed in the top cover layer.

9. A bonding structure, comprising a plurality of wafers bonded to each other in a direction perpendicular to the wafers, at least one of the plurality of wafers being a semiconductor wafer comprising:
a semiconductor substrate,
a device structure on the semiconductor substrate, and an interconnection structure for the device structure,
a top cover layer covering the interconnection structure,
a bonding pad disposed in the top cover layer, wherein the bonding pad is arranged in contact with and is connected to the interconnection structure, and
a bonding alignment mark disposed in the top cover layer;
wherein a pattern of the bonding alignment mark comprises a plurality of sub-patterns, each of the plurality of sub-patterns comprises an array of dots, and a smallest distance among the plurality of sub-patterns is greater than a distance between centers of adjacent dots in the array of one of the plurality of sub-patterns.

10. The bonding structure according to claim 9 , wherein the pattern of the bonding alignment mark is centrally symmetric.

11. The bonding structure according to claim 10 , wherein the plurality of sub-patterns comprise sub-patterns which form a surrounding pattern, and sub-patterns which form a central pattern, and the central pattern is surrounded by the surrounding pattern.

12. The bonding structure according to claim 11 , wherein the surrounding pattern includes a sub-pattern having a polygonal shape.

13. The bonding structure according to claim 11 , wherein the surrounding pattern has a polygonal shape, and the sub-patterns forming surrounding pattern have a strip shape.

14. The bonding structure according to claim 10 , wherein the pattern of the bonding alignment mark comprises multiple regions, and sub-patterns in adjacent regions extend in different directions.

15. The bonding structure according to claim 9 , wherein the semiconductor wafer comprises chip regions arranged in an array, the device structure is located in the chip regions, and the bonding alignment mark is located in scribe lines between adjacent chip regions.

16. The bonding structure according to claim 9 , wherein each dot in the array corresponds to a circular cylinder, an elliptical cylinder or a rectangular cylinder.

17. A wafer bonding method, comprising:
providing a to-be-bonded wafer, wherein the to-be-bonded wafer is a semiconductor wafer comprising:
a semiconductor substrate,
a device structure on the semiconductor substrate, and an interconnection structure for the device structure,
a top cover layer covering the interconnection structure,
a bonding pad disposed in the top cover layer, wherein the bonding pad is arranged in contact with and is connected to the interconnection structure, and
a bonding alignment mark disposed in the top cover layer, wherein a pattern of the bonding alignment mark comprises a plurality of sub-patterns, each of the plurality of sub-patterns comprises an array of dots, and a smallest distance among the plurality of sub-patterns is greater than a distance between centers of adjacent dots in the array of one of the plurality of sub-patterns;

performing alignment by using the bonding alignment mark in the to-be-bonded wafer; and
bonding the to-be-bonded wafer to another wafer.

Assignees

• Wuhan Xinxin Semiconductor Mfg

Inventors

• Zhou Yunpeng
• Guo Wanli
• Hu Xing
• Huang Yuheng

Classifications

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/921

  Structures or relative sizes of bond pads · CPC title

• H10W46/301

  for alignment · CPC title