Method for automatically adjusting gain of multi-stage equalizer of serial data receiver

Patent metadata

Field	Value
Publication number	US-11063792-B2
Application number	US-201916729430-A
Country	US
Kind code	B2
Filing date	Dec 29, 2019
Priority date	Dec 29, 2018
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

The invention provides a method for automatically adjusting the gain of a multi-stage equalizer of a serial data receiver, the serial data receiver provides a gain circuit, the gain circuit comprises a multi-stage equalization circuit, and each stage of equalization circuit is arranged in series; the method comprises: Step S1, setting corresponding serial numbers for each stage of equalization circuit in sequence; Step S2, selecting an equalization circuit corresponding to the serial number from the gain circuit according to a preset rule; Step S3, sequentially adjusting the selected equalization circuits of each stage according to the sequence of the serial numbers to obtain corresponding standard adjustment values; and Step S4, adjusting the equalization circuit greater than or equal to the corresponding serial number according to the standard adjustment value. The method has the benefits that the optimal compensation for the signal is realized.

First claim

What is claimed is:

1. A method for automatically adjusting a gain of a multi-stage equalizer of a serial data receiver, applied to the serial data receiver, wherein,
the serial data receiver comprises a gain circuit, the gain circuit comprises a multi-stage equalization circuit, and each stage of the equalization circuit is arranged in series;
the method for automatically adjusting comprises:
Step S 1 , setting corresponding reference numbers for each stage of the equalization circuit in sequence;
Step S 2 , selecting an equalization circuit corresponding to the reference numbers from the gain circuit according to a preset rule;
Step S 3 , sequentially adjusting the selected equalization circuit of each stage according to the sequence of the reference numbers to obtain corresponding standard adjustment values; and
Step S 4 , adjusting the equalization circuit greater than or equal to the corresponding reference number according to the standard adjustment values;
the equalization circuit is provided with a standard gain value;
Step S 3 further comprises:
Step S 31 , comparing a gain value of the current equalization circuit with the standard gain value;
Step S 32 , setting the gain value of the current equalization circuit to the standard gain value, and executing Step S 4 ;
Step S 33 , adjusting the gain value of the current equalization circuit until the gain value of the current equalization circuit is set to the standard gain value, then executing Step S 4
during executing Step S 31 , if the gain value of the current equalization circuit is equal to the standard gain value, executing Step S 32 ;
if the gain value of current the equalization circuit is not equal to the standard gain value, executing Step S 33 .

2. The method for automatically adjusting according to claim 1 , wherein the preset rule in Step S 2 is to select the equalization circuit corresponding to the reference number at a preset interval.

3. The method for automatically adjusting according to claim 2 , wherein the preset interval is more than one of the equalization circuits.

4. The method for automatically adjusting according to claim 1 , wherein the preset rule in Step S 2 comprises:
Step C 1 , counting the number of the equalization circuits;
Step C 2 , calculating the reference number of the selected equalization circuit using the following formula according to the number;

{

A
=
1

,

m
=
1

A
=

2

m
-
1

-
1

2
m

-
1

×
n

,

m
≥
2

wherein A represents the reference number of the selected equalization circuit, when A is not an integer, A is set to an integer closest to A and greater than A;
m represents a current round of selection; and
n represents the number of the equalization circuits.

5. The method for automatically adjusting according to claim 1 , wherein the equalization circuit comprises two branch circuits, one end of each of the two branch circuits is connected to VDD, and the other end of each of the two branch circuits is connected to GND;
a NMOS transistor is arranged on each of the two branch circuits;
a resistor is connected between a drain of the NMOS transistor of each of the two branch circuits and VDD;
an output point is arranged between the resistor of each of the two branch circuits and the drain of the NMOS transistor, and a branch capacitor is connected between the output point and GND;
a current source is connected between a source of the NMOS transistor of each of the two branch circuits and GND;
a first access point is arranged between the source of the NMOS transistor of each of the two branch circuits and the current source, and an adjusting resistor is connected between the two first access points;
a second access point is arranged between the first access point of each of the two branch circuits and the current source, and an adjusting capacitor is connected between the two second access points; and/or
the equalization circuit is provided with a transfer function expressed by the following formula:

H
⁡

(
S
)

=

g
m

C
p

⁢

s
+

1

R
s

⁢

C
s

(

s
+

1
+

g
m

⁢

R
s

/
2

R
s

⁢

Assignees

• Amlogic Shanghai Co Ltd

Inventors

• Zou Weihua
• Shi Ming

Classifications

• H03F3/45197

  Pl types (H03F3/45224, H03F3/45251 take precedence) · CPC title

• H04L25/03885 Primary

  adaptive · CPC title