Hybrid optical and EUV lithography

Patent metadata

Field	Value
Publication number	US-11061315-B2
Application number	US-201816191589-A
Country	US
Kind code	B2
Filing date	Nov 15, 2018
Priority date	Nov 15, 2018
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

Methods pattern a sacrificial material on an etch mask into mandrels using optical mask lithography, form a conformal material and a fill material on the mandrels, and planarize the fill material to the level of the conformal material. Such methods pattern the fill material into first mask features using extreme ultraviolet (EUV) lithography. These methods partially remove the conformal material to leave the conformal material on the sidewalls of the mandrels as second mask features. Spaces between the first mask features and the second mask features define an etching pattern. The spacing distance of the mandrels is larger than the spacing distance of the second mask features. Such methods transfer the etching pattern into the etch mask material, and subsequently transfer the etching pattern into an underlying layer. Openings in the underlying layer are filled with a conductor to form wiring in the etching pattern.

First claim

What is claimed is:

1. A method comprising:
patterning a sacrificial material on an etch mask material into mandrels using optical lithography, wherein the etch mask material is on an underlying layer;
forming a conformal material on the mandrels and the etch mask material;
forming a fill material on the conformal material;
patterning the fill material into first mask features using extreme ultraviolet (EUV) lithography;
partially removing the conformal material to leave the conformal material on sidewalls of the mandrels as second mask features, wherein spaces between the first mask features and the second mask features define an etching pattern;
removing portions of the etch mask material not protected by the first mask features and the second mask features to transfer the etching pattern into the etch mask material;
removing the first mask features and second mask features; and
etching the underlying layer through the etching pattern in the etch mask material to transfer the etching pattern into the underlying layer.

2. The method according to claim 1 , wherein a first spacing distance of the mandrels is twice as large as a second spacing distance of the second mask features.

3. The method according to claim 1 , wherein a first spacing distance of the mandrels is 3 times larger than the first mask features and the second mask features defining spacing distance of the etching pattern, and wherein a second spacing distance of the second mask features is 1.5 times larger than spaces between the first mask features and the second mask features defining spacing distance of the etching pattern.

4. The method according to claim 1 , wherein the patterning of the fill material leaves the fill material between locations of the mandrels.

5. The method according to claim 1 , further comprising planarizing the fill material to a level of the conformal material before performing the patterning of the fill material.

6. The method according to claim 1 , wherein ones of the first mask features are formed parallel to the second mask features.

7. The method according to claim 1 , wherein ones of the first mask features are formed co-linear with the second mask features.

8. A method comprising:
patterning a silicon layer on a silicon nitride layer into mandrels using light-blocking mask optical lithography, wherein the silicon nitride layer is on a dielectric layer;
forming an oxide material on the mandrels and the silicon nitride layer;
forming a spin-on-glass material on the oxide material;
patterning the spin-on-glass material into first mask features using extreme ultraviolet (EUV) reflective lithography, wherein the first mask features include a lower layer of the oxide material between the silicon nitride layer and the spin-on-glass material that is distal to the silicon nitride layer;
partially etching the oxide material using the silicon nitride layer as an etch stop to leave the oxide material on sidewalls of the mandrels as second mask features;
removing the mandrels, wherein spaces between the first mask features and the second mask features define an etching pattern, and wherein a first spacing distance of the mandrels is larger than a second spacing distance of the second mask features;
removing portions of the silicon nitride layer not protected by the first mask features and the second mask features to transfer the etching pattern into the silicon nitride layer;
removing the first mask features and second mask features;
etching the dielectric layer through the etching pattern in the silicon nitride layer to transfer openings matching the etching pattern into the dielectric layer; and
filling the openings with a metal to form wiring in the dielectric layer having a wiring pattern matching the etching pattern.

9. The method according to claim 8 , wherein a first spacing distance of the mandrels is twice as large as a second spacing distance of the second mask features.

10. The method according to claim 8 , wherein a first spacing distance of the mandrels is 3 times larger than spacing distance of the etching pattern, and wherein a second spacing distance of the second mask features is 1.5 times larger than the spacing distance of the etching pattern.

11. The method according to claim 8 , wherein the patterning of the spin-on-glass material leaves the spin-on-glass material between locations of the mandrels.

12. The method according to claim 8 , further comprising planarizing the spin-on-glass material using chemical mechanical planarization (CMP) to a level of the oxide material before performing the patterning of the spin-on-glass material.

13. The method according to claim 8 , wherein ones of the first mask features are formed between and parallel to the second mask features.

14. The method according to claim 8 , wherein ones of the first mask features are formed co-linear with the second mask features.

15. An integrated circuit structure comprising:
a wiring layer within a plurality of layers,
wherein the wiring layer comprises wiring lines within an insulator,
wherein the wiring lines comprise first conductive lines and second conductive lines,
wherein the first conductive lines are wider than the second conductive lines, and
wherein the first conductive lines have a larger number of irregularities relative to the second conductive lines,
wherein the first conductive lines result from first mask features being formed using extreme ultraviolet (EUV) reflective lithography,
wherein the second conductive lines result from second mask features being formed using optical lithography and sidewall image transfer (SIT) techniques,
wherein the first mask features are formed using an EUV reflective lithography patterned and planarized fill material on a conformal material,
wherein the conformal material is formed on an etch mask,
wherein the second mask features are formed as sidewall features on sacrificial mandrels on the etch mask using the SIT techniques,
wherein the sacrificial mandrels are formed using the optical lithography, and
wherein the etch mask is used to pattern the first conductive lines and the second conductive lines.

16. The integrated circuit structure according to claim 15 , wherein the larger number of irregularities include inconsistently shaped sidewalls along lengths of the first conductive lines relative to shapes of sidewalls of the second conductive lines.

17. The integrated circuit structure according to claim 15 , wherein the larger number of irregularities include the first conductive lines having relatively less consistent widths relative to widths of the second conductive lines.

18. The integrated circuit structure according to claim 15 , wherein the larger number of irregularities include ones of the second conductive lines having a first sidewall with the larger number of irregularities and a second sidewall lacking the larger number of irregularities.

19. The integrated circuit structure according to claim 15 , wherein a pitch of the first conductive lines is 1.5 times a pitch of the second conductive lines.

20. The integrated circuit structure according to claim 15 , further comprising a liner between the insulator and the wiring lines.

Assignees

• Globalfoundries Us Inc

Inventors

• Zeng Jia
• Bouche Guillaume
• Sun Lei
• Han Geng

Classifications

• H10P76/4088 Primary

  Processes for improving the resolution of the masks · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/696

  Process specially adapted to improve the resolution of the mask · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/73

  using masks for insulating materials · CPC title