Method of producing a wired circuit board

Patent metadata

Field	Value
Publication number	US-11058002-B2
Application number	US-201816649825-A
Country	US
Kind code	B2
Filing date	Sep 6, 2018
Priority date	Sep 29, 2017
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

A method for producing a wired circuit board, the method including the steps of: a first step of providing an insulating layer having an opening penetrating in the thickness direction at one side surface in the thickness direction of the metal plate, a second step of providing a first barrier layer at one side surface in the thickness direction of the metal plate exposed from the opening by plating, a third step of providing a second barrier layer continuously at one side in the thickness direction of the first barrier layer and an inner surface of the insulating layer facing the opening, a fourth step of providing a conductor layer so as to contact the second barrier layer, and a fifth step of removing the metal plate by etching.

First claim

The invention claimed is:

1. A method of producing a wired circuit board, the method including the steps of:
a first step of providing an insulating layer having an opening penetrating in a thickness direction of the insulating layer at one side surface in a thickness direction of a metal plate,
a second step of providing a first barrier layer at one side surface in the thickness direction of the metal plate exposed from the opening by plating, the first barrier layer being positioned at a lower end edge in the opening so as to take up only a portion of the opening in a thickness direction of the opening as compared to a thickness of the insulating layer,
a third step of providing a second barrier layer continuously at one side in a thickness direction of the first barrier layer and an inner, side wall surface of the insulating layer which forms the opening,
a fourth step of providing a conductor layer so as to contact the second barrier layer, and
a fifth step of removing the metal plate by etching.

2. The method of producing a wired circuit board according to claim 1 , wherein
in the third step, the second barrier layer is provided at one side surface in the thickness direction of the first barrier layer.

3. The method of producing a wired circuit board according to claim 1 , wherein
in the third step, the second barrier layer is further provided at one side surface in the thickness direction of the insulating layer surrounding the opening.

4. The method of producing a wired circuit board according to claim 1 , wherein
in the first step, the opening is provided so that the inner, side wall surface of the insulating layer has a tapered shape inclining relative to the thickness direction of the insulating layer.

5. The method of producing a wired circuit board described in claim 1 , wherein
in the third step, the second barrier layer is formed by sputtering.

6. The method of producing a wired circuit board according to claim 1 , wherein
a material of the second barrier layer is chromium.

7. The method of producing a wired circuit board according to claim 1 , wherein
the conductor layer has a thickness of 12 μm or less.

8. The method of producing a wired circuit board according to claim 1 , wherein
the first barrier layer has a thickness of 0.05 μm or more and 5 μm or less.

9. The method of producing a wired circuit board according to claim 1 , wherein
the first barrier layer has a thickness of 0.2 μm or more and 5 μm or less.

Assignees

• Nitto Denko Corp

Inventors

• Shibata Shusaku
• Takakura Hayato
• Ito Masaki
• Kawamura Yoshihiro
• Wakaki Shuichi

Classifications

• Y10T29/5317

  Laminated device · CPC title

• H05K3/0023

  by exposure and development of a photosensitive insulating layer · CPC title

• H05K3/048

  using a lift-off resist pattern or a release layer pattern · CPC title

• H05K3/4076

  by thin-film techniques · CPC title

• H05K3/429

  Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers · CPC title