Printed wiring board

Patent metadata

Field	Value
Publication number	US-9723729-B2
Application number	US-201514920974-A
Country	US
Kind code	B2
Filing date	Oct 23, 2015
Priority date	Oct 23, 2014
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A printed wiring board includes a substrate, a first conductor layer formed on first surface of the substrate, a second conductor layer formed on second surface of the substrate, a through-hole conductor penetrating through the substrate and connecting the first and second conductor layers, a build-up layer formed on the second surface of the substrate and including conductor layers, insulating layers and via conductors, and a first insulating layer formed on the first surface the substrate and covering the first conductor layer. The substrate has a cavity penetrating through the first insulating layer and substrate and exposing the build-up layer on the substrate, the via conductors include a lowermost via conductor having a bottom portion exposed at bottom of the cavity, and the bottom portion of the lowermost via conductor is recessed relative to surface of a lowermost insulating layer in the build-up layer at the bottom of the cavity.

First claim

What is claimed is:

1. A printed wiring board, comprising:
a substrate;
a first conductor layer formed on a first surface of the substrate;
a second conductor layer formed on a second surface of the substrate;
a through-hole conductor penetrating through the substrate such that the through-hole conductor is connecting the first conductor layer and the second conductor layer;
a build-up layer formed on the second surface of the substrate and comprising a plurality of conductor layers, a plurality of insulating layers, and a plurality of via conductors connecting the conductor layers through the insulating layers; and
a first insulating layer formed on the first surface the substrate such that the first insulating layer is covering the first conductor layer on the substrate,
wherein the substrate has a cavity penetrating through the first insulating layer and the substrate such that the cavity is exposing a mounting area portion of the build-up layer on the second surface of the substrate, the build-up layer is formed such that the plurality of via conductors includes a plurality of mounting via conductors positioned in the mounting area portion and having a plurality of bottom portions exposed in the cavity, and the plurality of mounting via conductor is formed such that each of the bottom portions of the mounting via conductors is recessed relative to a surface of a lowermost insulating layer in the build-up layer at a bottom of the cavity.

2. A printed wiring board according to claim 1 , wherein the plurality of mounting via conductors is formed such that each of the bottom portions is recessed in a range of 0.1 μm to 5 μm relative to the surface of the lowermost insulating layer in the build-up layer at the bottom of the cavity.

3. A printed wiring board according to claim 2 , wherein the plurality of insulating layers in the build-up layer does not include core material and includes inorganic filler in an amount of 40 wt % to 80 wt %.

4. A printed wiring board according to claim 2 , wherein the through-hole conductor is formed such that the through-hole conductor comprises a taper portion tapering from the first surface toward the second surface of the substrate and a taper portion tapering from the second surface toward the first surface of the substrate.

5. A printed wiring board according to claim 2 , wherein the substrate has the cavity formed such that the cavity is tapering from the first surface toward the second surface of the substrate.

6. A printed wiring board according to claim 1 , further comprising:
a plurality of surface treatment layer portions formed on the bottom portions of the mounting via conductors, respectively,
wherein each of the surface treatment layer portions comprises one of a structure comprising a Ni layer, a Pd layer and a Au layer, a structure comprising a Ni layer and a Au layer, and a structure comprising a Pd layer and a Au layer.

7. A printed wiring board according to claim 6 , wherein the plurality of surface treatment layer portions is formed on the bottom portions of the mounting via conductors such that the plurality of surface treatment layer portions is projecting in a range of 3 μm to 10 μm relative to the surface of the lowermost insulating layer in the build-up layer at the bottom of the cavity.

8. A printed wiring board according to claim 6 , wherein the plurality of surface treatment layer portions is formed on the bottom portions of the mounting via conductors such that the plurality of surface treatment layer portions is covering the bottom portions and portions of side surfaces of the mounting via conductors.

9. A printed wiring board according to claim 1 , further comprising:
a plurality of surface treatment layer portions formed on the bottom portions of the mounting via conductors, respectively,
wherein each of the surface treatment layer portions comprises a structure comprising a Ni layer, a Pd layer and a Au layer such that the Ni layer has a thickness in a range of 5.0 μm to 10.0 μm, the Pd layer has a thickness in a range of 0.02 μm to 0.10 μm and the Au layer has a thickness in a range of 0.02 μm to 0.10 μm.

10. A printed wiring board according to claim 1 , wherein the plurality of insulating layers in the build-up layer does not include core material and includes inorganic filler in an amount of 40 wt % to 80 wt %.

11. A printed wiring board according to claim 1 , wherein the through-hole conductor is formed such that the through-hole conductor comprises a taper portion tapering from the first surface toward the second surface of the substrate and a taper portion tapering from the second surface toward the first surface of the substrate.

12. A printed wiring board according to claim 1 , wherein the plurality of via conductors in the build-up layer includes a plurality of via conductors forming a stack via conductor structure.

13. A printed wiring board according to claim 1 , wherein the substrate has the cavity formed such that the cavity is tapering from the first surface toward the second surface of the substrate.

14. A printed wiring board according to claim 1 , further comprising:
a plurality of surface treatment layer portions formed on the bottom portions of the mounting via conductors, respectively.

15. A printed wiring board according to claim 14 , wherein the plurality of surface treatment layer portions is formed on the bottom portions of the mounting via conductors such that each of the surface treatment layer portions is projecting in a range of 3 μm to 10 μm relative to the surface of the lowermost insulating layer in the build-up layer at the bottom of the cavity.

16. A printed wiring board according to claim 14 , wherein the plurality of surface treatment layer portions is formed on the bottom portions of the mounting via conductors such that the plurality of surface treatment layer portions is covering the bottom portions and portions of side surfaces of the mounting via conductors.

17. A printed wiring board according to claim 1 , further comprising:
a plurality of surface treatment layer portions formed on the bottom portions of the mounting via conductors, respectively,
wherein each of the surface treatment layer portions is one of a structure consisting of a Ni layer, a Pd layer and a Au layer, a structure consisting of a Ni layer and a Au layer, and a structure consisting of a Pd layer and a Au layer.

18. A printed wiring board according to claim 17 , wherein the plurality of surface treatment layer portions is formed on the bottom portions of the mounting via conductors such that each of the surface treatment layer portions is projecting in a range of 3 μm to 10 μm relative to the surface of the lowermost insulating layer in the build-up layer at the bottom of the cavity.

19. A printed wiring board according to claim 17 , wherein the plurality of surface treatment layer portions is formed on the bottom portions of the mounting via conductors such that the plurality of surface treatment layer portions is covering the bottom portions and portions of side surfaces of the mounting via conductors.

20. A printed wiring board according to claim 1 wherein each of the mounting via conductors in the build-up layer comprises an electroless plating portion and an electrolytic plating portion such that each of the bottom portions a surface of the electrolytic plating portion exposed from the electroless plating portion.

Assignees

• Ibiden Co Ltd

Inventors

• Furusawa Takeshi
• Noda Kota

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title