Heterolithic microwave integrated circuits including gallium-nitride devices on intrinsic semiconductor

Patent metadata

Field	Value
Publication number	US-11056483-B2
Application number	US-201815875406-A
Country	US
Kind code	B2
Filing date	Jan 19, 2018
Priority date	Jan 19, 2018
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

Apparatus and methods relating to heterolithic microwave integrated circuits HMICs are described. An HMIC can include different semiconductor devices formed from different semiconductor systems in different regions of a same substrate. An HMIC can also include bulk regions of low-loss electrically-insulating material extending through the substrate and located between the different semiconductor regions. Passive RF circuit elements can be formed on the low-loss electrically-insulating material.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first region of the integrated circuit, the first region containing a p-i-n or n-i-p semiconductor diode formed on a substrate from a first semiconductor material of a first base elemental composition that is common with the substrate;
a second region of the integrated circuit, the second region containing a transistor formed on the substrate from gallium-nitride material, the composition of the gallium-nitride material being different than the first semiconductor material of the first base elemental composition and the substrate; and
a third region of the integrated circuit containing an electrically-insulating dielectric material that extends through the substrate and separates the substrate between the first region and the second region.

2. The integrated circuit of claim 1 , further comprising an intrinsic region of the first semiconductor material located between the gallium-nitride material and the substrate in the second region.

3. The integrated circuit of claim 1 , wherein the first semiconductor material has a base elemental composition of silicon.

4. The integrated circuit of claim 1 , wherein the gallium-nitride material comprises gallium-nitride (GaN).

5. The integrated circuit of claim 1 , wherein the transistor comprises a high-electron-mobility transistor.

6. The integrated circuit of claim 1 , further comprising at least one conductive interconnect formed over the third region.

7. The integrated circuit of claim 1 , further comprising at least a portion of one passive circuit element formed over the third region.

8. The integrated circuit of claim 7 , wherein the passive circuit element is an inductor.

9. The integrated circuit of claim 1 , further comprising:
a ground plane formed on a back side of the substrate below the first region, second region, and third region; and
a passivation layer formed over the first region, second region, and third region.

10. The integrated circuit of claim 1 , wherein a thickness of the substrate is between 50 microns and 200 microns.

11. The integrated circuit of claim 1 , wherein the electrically-insulating dielectric material extends entirely through the substrate.

12. The integrated circuit of claim 1 , wherein the substrate comprises a semiconductor.

13. A method of making a heterolithic microwave integrated circuit, the method comprising:
forming a first semiconductor device from a first semiconductor material in a first region of a wafer;
forming a second semiconductor material on the first semiconductor material in a second region of the wafer, the second semiconductor material having a different base elemental composition than the first semiconductor material;
forming a second semiconductor device from the second semiconductor material;
etching a cavity in a third region of the wafer;
filling the cavity with an electrically-insulating material;
planarizing the electrically-insulating material; and
removing a portion of a backside of the wafer to expose the electrically-insulating material.

14. The method of claim 13 , wherein forming the first semiconductor device comprises forming a semiconductor diode and wherein the first semiconductor material has a base elemental composition of silicon.

15. The method of claim 14 , wherein forming the second semiconductor device comprises forming a transistor and wherein the second semiconductor material has a base elemental composition of gallium-nitride material.

16. The method of claim 13 , wherein forming the second semiconductor material comprises epitaxially growing the second semiconductor material on an intrinsic region of the first semiconductor material.

17. The method of claim 13 , further comprising covering the second semiconductor material with a protective layer before filling the cavity.

18. The method of claim 13 , wherein filling the cavity comprises forcing into the cavity under pressure the electrically-insulating material that is heated above its glass transition temperature.

19. The method of claim 13 , wherein removing a portion of the backside of the wafer comprises removing regions at a bottom of the cavity that are not filled with the electrically-insulating material and planarizing a backside of the wafer.

20. The method of claim 13 , further comprising forming a conductive interconnect over the electrically-insulating material in the third region.

21. The method of claim 13 , further comprising forming at least a portion of a passive device over the electrically-insulating material in the third region.

22. A packaged integrated circuit, comprising:
an enclosure; and
an integrated circuit within the enclosure, the integrated circuit comprising:
a first region of the integrated circuit, the first region containing a p-i-n or n-i-p semiconductor diode formed on a substrate from a first semiconductor material of a first base elemental composition that is common with the substrate;
a second region of the integrated circuit, the second region containing a transistor formed on the substrate from gallium-nitride material, the composition of the gallium-nitride material being different than the first semiconductor material of the first base elemental composition and the substrate; and
a third region of the integrated circuit containing an electrically-insulating dielectric material that extends through the substrate and separates the substrate between the first region and the second region.

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Boles Timothy E
• Struble Wayne Mack

Classifications

• H10P14/2908

  Nitrides · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W44/20 Primary

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title