Structures and methods for reliable packages

Patent metadata

Field	Value
Publication number	US-11056390-B2
Application number	US-201916718820-A
Country	US
Kind code	B2
Filing date	Dec 18, 2019
Priority date	Jun 24, 2015
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

First claim

What is claimed is:

1. A stacked device comprising:
a first semiconductor element having a first upper surface, a first lower surface, and a first side surface extending between the first upper surface and the first lower surface;
a second semiconductor element stacked on the first semiconductor element, the second semiconductor element having a second upper surface, a second lower surface, and a second side surface extending between the second upper surface and the second lower surface;
an interconnection layer disposed between the first upper surface of the first semiconductor element and the second lower surface of the second semiconductor elements, the interconnection layer having a third upper surface, a third lower surface, and a third side surface extending between the third upper surface and the third lower surface; and
an encapsulation layer extending along the first side surface of the first semiconductor element, the second side surface of the second semiconductor element, and the third side surface of the interconnection layer.

2. The stacked device of claim 1 , further comprising a plurality of metallic vias disposed through the second semiconductor element from the second upper surface to the second lower surface of the second semiconductor element.

3. The stacked device of claim 2 , further comprising a second plurality of metallic vias disposed through the first semiconductor element.

4. The stacked device of claim 1 , wherein the encapsulation layer seamlessly and continuously extends across the respective first, second, and third side surfaces of the first semiconductor element, the second semiconductor element, and the interconnection layer.

5. The stacked device of claim 1 , wherein the encapsulation layer further extends over the second upper surface of the second semiconductor element, the second upper surface transverse to the second side surface of the second semiconductor element.

6. The stacked device of claim 1 , wherein the first side surface of the first semiconductor element is laterally inset relative to the second side surface of the second semiconductor element.

7. The stacked device of claim 1 , wherein a lateral footprint of the first semiconductor element is less than a lateral footprint of the second semiconductor element.

8. The stacked device of claim 1 , wherein the first side surface of the first semiconductor element is flush with the second side surface of the second semiconductor element.

9. The stacked device of claim 8 , wherein the first side surface of the first semiconductor element, the second side surface of the second semiconductor element, and the third side surface of the interconnection layer comprise etched surfaces.

10. The stacked device of claim 8 , wherein the first upper surface and the second lower surface are mounted to the interconnection layer, and wherein the encapsulation layer extends from the second major lateral surface of the first semiconductor element to the second major lateral surface of the second semiconductor element.

11. The stacked device of claim 10 , further comprising a second interconnection layer on the second upper surface of the second semiconductor element.

12. The stacked device of claim 11 , further comprising a third semiconductor element, the first semiconductor element stacked on the third semiconductor element.

13. The stacked device of claim 1 , wherein the third side surface of the interconnection layer is flush with the respective first and second side surfaces of one of the first and second semiconductor elements.

14. The stacked device of claim 1 , wherein the third side surface of the interconnection layer is flush with the respective first and second side surfaces of both the first and second semiconductor elements.

15. The stacked device of claim 1 , wherein a side surface of the encapsulation layer comprises a cut surface that is flush across the first and second semiconductor elements.

16. The stacked device of claim 1 , wherein at least one of the first and second semiconductor elements comprises a chip device.

17. The stacked device of claim 1 , wherein the interconnection layer comprises a back end-of-line layer (BEOL).

18. The stacked device of claim 1 , wherein the interconnection layer comprises a redistribution layer (RDL).

19. A stacked device comprising:
a first semiconductor element;
a second semiconductor element stacked on the first semiconductor element, the second semiconductor element comprising a plurality of metallic vias disposed through the second semiconductor element, the first and second semiconductor element comprising respective first and second major lateral surfaces, the respective first major lateral surfaces facing one another and the respective second major lateral surfaces facing away from one another, each of the first and second semiconductor elements comprising a respective side surface extending between the respective first and second major lateral surfaces; and
an encapsulation layer extending along the respective side surfaces of the first semiconductor element and the second semiconductor element, the encapsulation layer extending from the second major lateral surface of the first semiconductor element to the second major lateral surface of the second semiconductor element.

20. The stacked device of claim 19 , further comprising an interconnection layer disposed between the first and second semiconductor elements.

21. The stacked device of claim 19 , wherein at least one of the first and second semiconductor devices comprises a chip device.

22. The stacked device of claim 19 , wherein the side surface of the first semiconductor element is laterally inset relative to the side surface of the second semiconductor element.

Assignees

• Invensas Corp

Inventors

• Uzoh Cyprian Emeka
• Gao Guilian
• Wang Liang
• Shen Hong
• Sitaram Arkalgud R

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title