ESD protection circuit with isolated SCR for negative voltage operation

Patent metadata

Field	Value
Publication number	US-11049852-B2
Application number	US-201816053985-A
Country	US
Kind code	B2
Filing date	Aug 3, 2018
Priority date	Nov 2, 2012
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a semiconductor body having a surface;
a first doped region having a first conductivity type and a first depth from the surface of the semiconductor body;
a second doped region having a second conductivity type formed within the first doped region;
a third doped region having the second conductivity type and a second depth from the surface of the semiconductor body, the third doped region being formed proximate the first doped region at a first time;
a fourth doped region having the first conductivity type formed within the third doped region;
a buried layer having the first conductivity type formed below the third doped region and electrically connected to the first doped region, wherein the first doped region extends to the buried layer; and
a fifth doped region formed at a second time laterally between and touching both the first doped region and the third doped region, wherein the fifth doped region has a third depth from the surface of the semiconductor body, the third depth being less than the first depth and greater than the second depth and wherein the fifth doped region has the second conductivity type and is electrically connected to the third doped region.

2. An integrated circuit as in claim 1 , further comprising shallow trench isolation regions, wherein no shallow trench isolation region is between the second doped region and the fourth doped region.

3. An integrated circuit as in claim 1 , comprising a sixth doped region having the second conductivity type formed between the second doped region and the buried layer and electrically connected to the second doped region.

4. An integrated circuit as in claim 1 , comprising a gate formed over a junction between the first doped region and the third doped region, wherein the gate is electrically connected to the second doped region.

5. An integrated circuit as in claim 1 , comprising:
a seventh doped region having the first conductivity type and electrically connected to the second doped region and the first doped region; and
an eighth doped region having the second conductivity type and electrically connected to the fourth doped region and the third doped region.

6. An integrated circuit as in claim 1 , further comprising a substrate having the second conductivity type, and wherein the third doped region is electrically isolated from the substrate by the first doped region and the buried layer.

7. An integrated circuit, comprising:
a semiconductor body having a surface and including substrate of a second conductivity type; and
semiconductor controlled rectifier including:
a first doped region having a first conductivity type and a first depth from the surface of the semiconductor body;
a second doped region having the second conductivity type formed within the first doped region;
a third doped region having the second conductivity type and a second depth from the surface of the semiconductor body, the third doped region formed proximate the first doped region;
a fourth doped region having the first conductivity type formed within the third doped region;
a buried layer having the first conductivity type formed in the substrate below the third doped region and electrically connected to the first doped region, wherein the first doped region extends to the buried layer; and
a fifth doped region formed laterally between and touching both the first doped region and the third doped region, wherein the fifth doped region has a third depth from the surface of the semiconductor body, the third depth being less than the first depth and greater than the second depth and wherein the fifth doped region has the second conductivity type and is electrically connected to the third doped region.

8. An integrated circuit as in claim 7 , further comprising shallow trench isolation regions, wherein no shallow trench isolation region is between the second doped region and the fourth doped region.

9. An integrated circuit as in claim 7 , comprising a sixth doped region having the second conductivity type formed between the second doped region and the buried layer and electrically connected to the second doped region.

10. An integrated circuit as in claim 7 , comprising a gate formed over a junction between the first doped region and the third doped region, wherein the gate is electrically connected to the second doped region.

11. An integrated circuit as in claim 7 , comprising:
a seventh doped region having the first conductivity type and electrically connected to the second doped region and the first doped region; and
an eighth doped region having the second conductivity type and electrically connected to the fourth doped region and the third doped region.

12. An integrated circuit as in claim 7 , wherein the third doped region is electrically isolated from the substrate by the first doped region and the buried layer.

13. An integrated circuit, comprising:
a semiconductor body having a surface and including a p-type substrate; and
semiconductor controlled rectifier including:
a first n-type doped region having a first depth from the surface of the semiconductor body;
a first p-type doped region formed within the first n-type doped region;
a second p-type doped region having a second depth from the surface of the semiconductor body and being formed proximate the first n-type doped region;
a second n-type doped region formed within the second p-type doped region;
a n-type buried layer formed in the substrate below the second p-type doped region and electrically connected to the first n-type doped region, wherein the first n-type doped region extends to the n-type buried layer; and
a third p-type doped region formed laterally between and touching both the first n-type doped region and the second p-type doped region, wherein the third p-type doped region has a third depth from the surface of the semiconductor body, the third depth being less than the first depth and greater than the second depth and wherein the third p-type doped region is electrically connected to the second p-type doped region.

14. An integrated circuit as in claim 13 , comprising a gate formed over a junction between the first n-type doped region and the second p-type doped region, wherein the gate is electrically connected to the first p-type doped region.

15. An integrated circuit as in claim 14 , comprising:
a third n-type doped region electrically connected to the first p-type doped region and the first n-type doped region; and
a fifth p-type doped region electrically connected to the second n-type doped region and the second p-type doped region.

16. An integrated circuit as in claim 15 , further comprising shallow trench isolation regions, wherein no shallow trench isolation region is between the first p-type doped region and the second n-type doped region.

17. An integrated circuit as in claim 16 , comprising a fourth p-type doped region formed between the first p-type doped region and the n-type buried layer and electrically connected to the first p-type doped region.

18. An integrated circuit as in claim 16 , wherein the second p-type doped region is electrically isolated from the substrate by the first n-type doped region and the n-type buried layer.

Assignees

• Texas Instruments Inc

Inventors

• Salman Akram A
• Farbiz Farzan
• Chatterjee Amitava
• Wu Xiaoju

Classifications

• H10D62/192

  Base regions of thyristors · CPC title

• H10D18/251 Primary

  Lateral thyristors · CPC title

• H10D18/211

  having built-in localised breakdown or breakover regions, e.g. self-protected against destructive spontaneous firing · CPC title

• H10D89/713 Primary

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H01L27/0262 Primary

  Electricity · mapped topic