Defect-location determination using correction loop for pixel alignment

Patent metadata

Field	Value
Publication number	US-11049745-B2
Application number	US-201916417645-A
Country	US
Kind code	B2
Filing date	May 21, 2019
Priority date	Oct 19, 2018
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

A method of semiconductor-wafer image alignment is performed at a semiconductor-wafer defect-inspection system. In the method, a semiconductor wafer is loaded into the semiconductor-wafer defect-inspection system. Pre-inspection alignment is performed for the semiconductor wafer. After performing the pre-inspection alignment, a first swath is executed to generate a first image of a first region on the semiconductor wafer. An offset of a target structure in the first image with respect to a known point is determined. Defect identification is performed for the first image, using the offset. After executing the first swath and determining the offset, a second swath is executed to generate a second image of a second region on the semiconductor wafer. While executing the second swath, run-time alignment of the semiconductor wafer is performed using the offset.

First claim

What is claimed is:

1. A semiconductor-wafer defect-inspection system, comprising:
a semiconductor-wafer inspection tool;
one or more processors; and
memory storing one or more programs for execution by the one or more processors, the one or more programs comprising instructions for:
performing pre-inspection alignment for a semiconductor wafer;
after performing the pre-inspection alignment, executing a first swath to generate a first image of a first region on the semiconductor wafer;
determining an offset of a target structure in the first image with respect to a known point;
performing defect identification for the first image, using the offset;
after executing the first swath and determining the offset, executing a second swath to generate a second image of a second region on the semiconductor wafer; and
while executing the second swath, performing run-time alignment of the semiconductor wafer using the offset.

2. The system of claim 1 , wherein:
the semiconductor wafer comprises a plurality of die having a common layout; and
the known point is a location of the target structure in the common layout, wherein the location of the target structure in the common layout is provided in a file that specifies the layout.

3. The system of claim 1 , wherein the known point is a center of the wafer.

4. The system of claim 3 , wherein the instructions for performing the pre-inspection alignment comprise instructions for calculating a location of the center of the wafer.

5. The system of claim 1 , wherein the instructions for performing run-time alignment of the semiconductor wafer using the offset comprise instructions for:
determining a rotational correction factor for the semiconductor wafer based at least in part on the offset; and
rotating the wafer or an image of the wafer by an amount corresponding to the rotational correction factor.

6. The system of claim 5 , wherein:
the instructions for executing the second swath comprise instructions for generating and buffering an image of a first die in the second region and an image of a second die in the second region; and
the instructions for determining the rotational correction factor for the semiconductor wafer comprise instructions for:
identifying a difference between a location of the target structure in the image of the first die in the second region and a location of the target structure in the image of the second die in the second region;
specifying a search window for the rotational correction factor based at least in part on the offset; and
searching within the search window for the rotational correction factor, in accordance with the identified difference.

7. The system of claim 6 , wherein the first die is adjacent to the second die in the second swath.

8. The system of claim 1 , wherein:
the semiconductor-wafer defect-inspection system comprises a time-domain-integration (TDI) camera;
the instructions for executing the first swath and the second swath comprise instructions for using the TDI camera to generate the first image and the second image; and
the instructions for performing run-time alignment of the semiconductor wafer using the offset comprise instructions for:
determining a scale factor for a die in the second region based at least in part on the offset, wherein the scale factor indicates a difference between a size of the die as measured while performing the run-time alignment and a known size of the die; and
adjusting a rate of operation of the TDI camera in accordance with the scale factor.

9. The system of claim 8 , wherein:
the instructions for executing the second swath comprise instructions for generating and buffering an image of a first die in the second region and an image of a second die in the second region; and
the instructions for determining the scale factor comprise instructions for:
identifying a difference between a location of the target structure in the image of the first die in the second region and a location of the target structure in the image of the second die in the second region;
specifying a search window for the scale factor based at least in part on the offset; and
searching within the search window for the scale factor, in accordance with the identified difference.

10. The system of claim 9 , wherein the first die is adjacent to the second die in the second region.

11. The system of claim 1 , wherein the one or more programs further comprise instructions for performing a second pre-inspection alignment for the semiconductor wafer after performing the initial pre-inspection alignment and before generating the first image, the instructions for performing the second pre-inspection alignment comprising instructions for:
executing a specified plurality of swaths to inspect a specified plurality of respective regions on the semiconductor wafer, the specified plurality of swaths comprising a first swath to be executed on a top half of the wafer and a second swath to be executed on a bottom half of the wafer; and
aligning the semiconductor wafer based on the execution of the specified plurality of swaths.

12. The system of claim 11 , the one or more programs further comprising instructions for periodically repeating the second pre-inspection alignment for the semiconductor wafer during inspection of the semiconductor wafer, wherein a respective instance of the second pre-inspection alignment to be performed during inspection of the semiconductor wafer is to be performed based at least in part on the offset.

13. The system of claim 11 , wherein the second swath is distinct from the specified plurality of swaths.

14. The system of claim 1 , wherein the offset is a first offset, the one or more programs further comprising instructions for:
determining a second offset of the target structure in the second image with respect to the known point;
performing defect identification for the second image, using the second offset;
after executing the second swath and determining the second offset, executing a third swath to generate a third image of a third region on the semiconductor wafer; and
while executing the third swath, performing run-time alignment of the semiconductor wafer using the second offset.

15. A method of semiconductor-wafer image alignment, comprising, at a semiconductor-wafer defect-inspection system:
loading a semiconductor wafer into the semiconductor-wafer defect-inspection system;
performing pre-inspection alignment for the semiconductor wafer;
after performing the pre-inspection alignment, executing a first swath to generate a first image of a first region on the semiconductor wafer;
determining an offset of a target structure in the first image with respect to a known point;
performing defect identification for the first image, using the offset;
after executing the first swath and determining the offset, executing a second swath to generate a second image of a second region on the semiconductor wafer; and
while executing a second swath, performing run-time alignment of the semiconductor wafer using the offset.

16. A non-transitory computer-readable storage medium storing one or more programs for execution by one or more processors of a semiconductor-wafer defect-inspection system, the one or more programs comprising instructions for:
performing pre-inspection alignment for a semiconductor wafer;
after performing the pre-inspection alignment, executing a first swath to generate a first image of a first region on the semiconductor wafer;
determining an offset of a target structure in the first image with respect to a known point;

Assignees

• Kla Tencor Corp
• Kla Corp

Inventors

• Dowling David
• Singh Tarunark
• Brauer Bjorn
• Bhattacharyya Santosh
• Mantiply Bryant
• Lee Hucheng
• Li Xiaochun
• Park Sangbong

Classifications

• H10P72/0616 Primary

  Monitoring of warpages, curvatures, damages, defects or the like · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10P74/235

  comprising optical enhancement of defects or not-directly-visible states · CPC title

• H10P72/06

  Apparatus for monitoring, sorting, marking, testing or measuring · CPC title