Digital measurement of DAC timing mismatch error

Patent metadata

Field	Value
Publication number	US-9735797-B2
Application number	US-201615360349-A
Country	US
Kind code	B2
Filing date	Nov 23, 2016
Priority date	Dec 15, 2015
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine timing mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology utilizes cross-correlation of each DAC unit elements (UEs) output to the entire modulator output to measure its timing mismatch error respectively. Specifically, the timing mismatch error is estimated using a ratio based on a peak value and a value for the next tap in the cross-correlation function. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

First claim

What is claimed is:

1. A method for measuring timing mismatch error, comprising:
applying a pseudo random dither signal to an input of an element under test of a feedback digital to analog converter (DAC), wherein the feedback DAC has an output which is coupled to an analog input of an analog to digital converter (ADC) having a feedback loop configuration and an input which is coupled to a digital output of the ADC;
determining a cross-correlation between the pseudo random dither signal and the digital output of the ADC; and
determining a timing mismatch error associated with the element under test of the feedback digital to analog converter based on the cross-correlation.

2. The method of claim 1 , further comprising:
shorting the analog input to the ADC to ground.

3. The method of claim 1 , wherein the pseudo random dither signal is a pseudo randomized sequence of bits.

4. The method of claim 1 , further comprising:
while the pseudo random dither signal is applied to the input of the element under test, the digital output of the ADC is applied to other elements of the feedback DAC.

5. The method of claim 1 , wherein determining the timing mismatch error further comprises determining the timing mismatch error based on a peak value and a value of a tap next to the peak value of the cross-correlation.

6. The method of claim 1 , wherein determining the timing mismatch error further comprises determining a ratio of a value of a tap next to a peak value of the cross-correlation and a sum of the peak value and the value of the tap next to the peak value.

7. The method of claim 1 , further comprising:
repeating the applying and the measuring for another element under test of the feedback DAC.

8. A circuit for measuring timing mismatch, comprising:
a cross correlation block for performing a cross-correlation of a pseudo random dither signal applied to an input of an element in a feedback digital to analog converter (DAC) and a digital output of an analog to digital converter (ADC) having the feedback DAC; and
a ratio function block for determining timing mismatch error based on a ratio defined by a peak value in a cross-correlation function determined by the cross correlation block and a value of a tap in the cross-correlation function adjacent to the peak value.

9. The circuit of claim 8 , further comprising:
a buffer for storing samples of the pseudo random dither signal and samples of digital output of the ADC collected when the pseudo random dither signal is applied to the input of the element under test.

10. The circuit of claim 8 , further comprising:
selection circuitry for applying either the pseudo random dither signal or a corresponding part of the digital output of the ADC to the input of the element under test.

11. The circuit of claim 8 , wherein the ratio is defined as a ratio of the value of the tap adjacent to the peak value to a sum of the peak value and the value of the tap adjacent to the peak value.

12. The circuit of claim 8 , further comprising:
a look up table for storing timing mismatch errors determined from ratios determined by the ratio function block for a plurality of DAC elements in the feedback DAC.

13. The circuit of claim 8 , further comprising:
a switch for shorting an analog input to the ADC to ground.

14. The circuit of claim 8 , further comprising:
a pseudo random number generator for providing a pseudo randomized sequence of bits as the pseudo random dither signal.

15. An apparatus comprising:
a quantizer for digitizing an analog input and generating a digital output;
a feedback digital to analog converter (DAC) receiving the digital output as input and providing a feedback signal to the analog input;
means for applying a pseudo random dither signal to a DAC element under test of the feedback DAC while a remainder of DAC elements of the feedback DAC receives the digital output;
means for determining a cross-correlation between the pseudo random dither signal with the digital output; and
means for determining timing mismatch error from the cross-correlation.

16. The apparatus of claim 15 , further comprising:
means for calibrating the feedback DAC based on timing mismatch error.

17. The apparatus of claim 15 , wherein means for determining timing mismatch error from the cross-correlation comprises:
means for determining a sliding dot product of the pseudo random dither signal and the digital output.

18. The apparatus of claim 15 , wherein means for determining timing mismatch error from the cross-correlation comprises:
means for determining a peak value of the cross-correlation and a value of a tap in the cross-correlation adjacent to the peak value.

19. The apparatus of claim 18 , wherein means for determining timing mismatch error from the cross-correlation further comprises:
means for determining a ratio of the value of the tap adjacent to the peak value to a sum of the peak value and the value of the tap adjacent to the peak value.

20. The apparatus of claim 15 , wherein the apparatus is a continuous-time delta-sigma modulator in a multi-stage delta sigma analog-to-digital converter.

Assignees

• Analog Devices Inc

Inventors

• Zhao Jialin
• Meng Qingdong
• Dong Yunzhi
• Silva Jose Barreiro

Classifications

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/1071 Primary

  Measuring or testing · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M1/1038 Primary

  by storing corrected or correction values in one or more digital look-up tables (H03M1/1057 takes precedence) · CPC title

• H03M1/16

  with scale factor modification, i.e. by changing the amplification between the steps {(H03M1/141 takes precedence)} · CPC title