Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11043567-B2
Application number	US-201816115390-A
Country	US
Kind code	B2
Filing date	Aug 28, 2018
Priority date	Nov 30, 2017
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A semiconductor device includes a substrate, a gate stack. The substrate includes a semiconductor fin. The gate stack is disposed on the semiconductor fin. The gate stack includes a dielectric layer disposed over the semiconductor fin, and a metal stack disposed over the dielectric layer and having a first metallic layer and a second metallic layer over the first metallic layer, and a gate electrode disposed over the metal stack. The first metallic layer and the second metallic layer have a first element, and a percentage of the first element in the first metallic layer is greater than that in the second metallic layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate comprising a semiconductor fin; and
a gate stack disposed on the semiconductor fin, wherein the gate stack comprises:
a dielectric layer disposed over the semiconductor fin;
a metal stack disposed over the dielectric layer and having a first metallic layer and a second metallic layer over the first metallic layer, wherein the first metallic layer is a metal compound of a first element and a second element and the second metallic layer is a single-element metal of the second element, and wherein the metal stack further comprises an oxide layer between the first metallic layer and the second metallic layer; and
a gate electrode disposed over the metal stack.

2. The semiconductor device of claim 1 , wherein the metal stack further comprises a third metallic layer having the first element over the second metallic layer, and the third metallic layer is a metal compound of the first element and the second element.

3. The semiconductor device of claim 2 , wherein the metal stack further comprises a fourth metallic layer having the first element over the third metallic layer, and a percentage of the first element in the fourth metallic layer is greater than that in the third metallic layer.

4. The semiconductor device of claim 2 , wherein a composition of the first metallic layer and a composition of the third metallic layer are the same.

5. The semiconductor device of claim 2 , wherein a composition of the first metallic layer and a composition of the third metallic layer are different.

6. The semiconductor device of claim 2 , wherein the dielectric layer is made of high-k material, the dielectric layer has a U-shape cross-section, and the dielectric layer is in contact with the semiconductor fin.

7. The semiconductor device of claim 1 , wherein the metal stack further comprises a third metallic layer having the first element over the second metallic layer, and a percentage of the first element in the third metallic layer is substantially equal to that in the first metallic layer.

8. The semiconductor device of claim 7 , wherein the third metallic layer is thicker than the first metallic layer.

9. The semiconductor device of claim 1 , wherein the oxide layer has a thickness in a range from about 5 Å to about 30 Å.

10. The semiconductor device of claim 9 , wherein thicknesses of the first and second metallic layers are in a range from about 5 Å to about 15 Å.

11. The semiconductor device of claim 1 , wherein thicknesses of the first and second metallic layers are in a range from about 5 Å to about 15 Å.

12. A semiconductor device, comprising:
a substrate comprising a semiconductor fin;
a plurality of spacers disposed over the semiconductor fin;
a dielectric layer disposed over the semiconductor fin and between the spacers; and
a work function metal stack comprising alternately stacked first work function metal layers and second work function metal layers, wherein the first work function metal layers have a composition of X a1 Y 1-a1 and the second work function metal layers have a composition of X a2 Y 1-a2 , and a1≠a2.

13. The semiconductor device of claim 12 , wherein the first and second work function metal layers have a U-shape cross-section.

14. The semiconductor device of claim 12 , wherein a1+a2=1.

15. The semiconductor device of claim 12 , wherein thicknesses of the first and second work function metal layers are in a range from about 5 Å to about 15 Å.

16. A method, comprising:
forming a dummy gate stack over a fin structure of a substrate;
forming gate spacers on opposite sidewalls of the dummy gate stack;
removing the dummy gate stack to form a trench between the gate spacers; and
after removing the dummy gate stack, forming a gate stack in the trench between the gate spacers, wherein forming the gate stack comprises:
forming a dielectric layer over the fin structure;
forming a first metallic layer having a first element;
forming a second metallic layer having the first element over the first metallic layer, wherein the first metallic layer has a composition of X a1 Y 1-a1 and the second metallic layer has a composition of X a2 Y 1-a2 , and a1+a2=1, and wherein forming the first and second metallic layers are in-situ performed in a same chamber; and
forming a gate electrode over the second metallic layer.

17. The method of claim 16 , further comprising forming the first metallic layer and the second metallic layer in an alternating manner.

18. The method of claim 16 , further comprising forming a third metallic layer having the first element over the first metallic layer, wherein a percentage of the first element in the third metallic layer is greater than that in the second metallic layer.

19. The method of claim 16 , wherein the first metallic layer is a compound, and the second metallic layer is a single element.

20. The method of claim 16 , further comprising exposing the second metallic layer to air.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiang Hsin-Che
• Tzeng Ju-Yuan
• Liang Chun-Sheng
• Yeh Chih-Yang
• Wang Shu-Hui
• Yeh Jeng-Ya David

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/44

  Conductive materials thereof · CPC title