Inductor design in active 3D stacking technology

Patent metadata

Field	Value
Publication number	US-11043470-B2
Application number	US-201916694476-A
Country	US
Kind code	B2
Filing date	Nov 25, 2019
Priority date	Nov 25, 2019
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.

First claim

What is claimed is:

1. A multi-chip device comprising:
a chip stack comprising a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate and a front side dielectric layer on a front side of the semiconductor substrate;
an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer of the first chip being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and
an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer of the first chip, the isolation wall comprising a through substrate via (TSV) through the semiconductor substrate of the first chip, the isolation wall being disposed around the inductor.

2. The multi-chip device of claim 1 , wherein the front side dielectric layer is an outermost dielectric layer in which metallization is disposed.

3. The multi-chip device of claim 1 , wherein the first chip is an input/output (I/O) chip.

4. The multi-chip device of claim 1 , wherein the semiconductor substrate comprises intrinsic silicon in a region of the semiconductor substrate corresponding with a position of the inductor.

5. The multi-chip device of claim 1 , wherein the semiconductor substrate of the first chip has a thickness less than or equal to 2.7 um.

6. The multi-chip device of claim 1 , wherein at least one of the plurality of chips comprises a processing integrated circuit.

7. The multi-chip device of claim 1 , further comprising a pattern ground shield (PGS) disposed in the front side dielectric layer of the first chip, wherein the isolation wall surrounds and is electrically connected to the PGS.

8. The multi-chip device of claim 1 , wherein the isolation wall further extends into a second chip bonded to the first chip.

9. The multi-chip device of claim 1 , wherein at least one chip of the plurality of chips further comprises:
one or more front side metallization layers disposed in the front side dielectric layer, the one or more front side metallization layers comprising a top metallization layer disposed distal from the semiconductor substrate of the respective chip; and
one or more backside metallization layers disposed in the backside dielectric layer, the one or more backside metallization layers comprising a bottom metallization layer disposed distal from the semiconductor substrate of the respective chip.

10. The multi-chip device of claim 1 , wherein the isolation wall extends through more than one of the plurality of chips.

11. A method for constructing a multi-chip device, the method comprising:
forming a stack of a plurality of chips comprising forming the plurality of chips, each chip comprising a semiconductor substrate and a front side dielectric layer on a front side of the semiconductor substrate, wherein forming a first chip of the plurality of chips includes:
forming an inductor disposed in a backside dielectric layer of the first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side; and
forming an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer of the first chip, the isolation wall comprising a through-substrate via (TSV) through the semiconductor substrate of the first chip, the isolation wall being disposed around the inductor.

12. The method of claim 11 , wherein the front side dielectric layer of the first chip is an outermost dielectric layer in which metallization is disposed.

13. The method of claim 11 , wherein the semiconductor substrate comprises intrinsic silicon in a region of the semiconductor substrate corresponding with a position of the inductor.

14. The method of claim 11 , wherein the semiconductor substrate has a thickness of less than or equal to 2.7 um.

15. The method of claim 11 , wherein the plurality of chips comprise Active-on-Active (AoA) chips.

16. The method of claim 11 , further comprising forming a pattern ground shield (PGS) disposed in the front side dielectric layer of the first chip, wherein the isolation wall surrounds and is electrically connected to the PGS.

17. The method of claim 11 , wherein the isolation wall further extends into a second chip bonded to the first chip.

18. The method of claim 11 , wherein the isolation wall extends through more than one of the plurality of chips.

19. A multi-chip device comprising:
a chip stack;
an inductor disposed in a backside dielectric layer of a first chip of the chip stack; and
an isolation wall extending from the backside dielectric layer of the first chip to a front side dielectric layer of the first chip, the isolation wall being disposed around the inductor.

20. The multi-chip device of claim 19 , further comprising a pattern ground shield (PGS) disposed in the front side dielectric layer of the first chip, wherein the isolation wall surrounds and is electrically connected to the PGS.

Assignees

• Xilinx Inc

Inventors

• Jing Jing
• Wu Shuxian
• Wu Xin X
• Frans Yohan

Classifications

• H10W70/095

  of vias therein · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title