Semiconductor device, electronic circuit having the same, and semiconductor device forming method

Patent metadata

Field	Value
Publication number	US-10446485-B2
Application number	US-201715858529-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Apr 7, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A semiconductor device includes: a plurality of first wires formed in a first layer and indicating fixed potentials; and an inductor formed in a second layer stacked on the first layer, and wiring widths of the first wires located within a range of a formation region of the inductor in a plan view among the plurality of first wires are formed narrower than wiring widths of the first wires located outside the range of the formation region of the inductor.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of first wires formed in a first layer and configured to indicate a fixed potential; and
an inductor formed in a second layer stacked on the first layer,
wherein a wiring width of the first wiring located within a range of a formation region of the inductor in a plan view among the plurality of first wires is formed narrower than a wiring width of the first wiring located outside the range of the formation region of the inductor.

2. The semiconductor device according to claim 1 , wherein the formation region of the inductor includes a region surrounded by an outer circumferential side of the inductor in the plan view.

3. The semiconductor device according to claim 1 , further comprising a guard ring arranged to surround the inductor in the second layer,
wherein the formation region of the inductor region surrounded by the guard ring in the plan view.

4. The semiconductor device according to claim 1 , wherein
the inductor is formed in a helical shape in the plan view, and
the formation region of the inductor is determined based on an inner diameter of the inductor in the plan view.

5. The semiconductor device according to claim 1 , wherein the plurality of first wires are configured to allow propagation of one of a power supply voltage and a ground voltage thereto.

6. The semiconductor device according to claim 1 , wherein the plurality of first wires are formed in slit shapes over the entire first layer.

7. The semiconductor device according to claim 1 , wherein the plurality of first wires are formed to short-circuit each other in the first layer located at a boundary line between the formation region and a non-formation region of the inductor in the plan view.

8. The semiconductor device according to claim 1 , wherein
the inductor is formed in a helical shape in the plane view and has a larger inner diameter than a predetermined inner diameter, and
a wiring width of the first wire located in a center region of the formation region of the inductor in the plan view among the plurality of first wires is formed wider than a wiring width of the first wiring located in a rest of the formation region of the inductor.

9. The semiconductor device according to claim 1 , wherein
the inductor is formed in a helical shape in the plan view and has a smaller inner diameter than a predetermined inner diameter, and
the plurality of first wires have a predetermined spatial region in the first layer located in a center region of the formation region of the inductor in the plan view.

10. The semiconductor device according to claim 1 , further comprising a plurality of second wires formed in the first layer and configured to indicate a fixed potential of a level different from that of the plurality of first wires,
wherein a wiring width of the second wiring located within the range of the formation region of the inductor in the plan view among the plurality of second wires is formed narrower than a wiring width of the second wiring located outside the range of the formation region of the inductor.

11. The semiconductor device according to claim 10 , wherein
the plurality of first wires are configured to allow propagation of a power supply voltage thereto, and
the plurality of second wires are configured to allow propagation of a ground voltage thereto.

12. The semiconductor device according to claim 10 , wherein the plurality of first wires and the plurality of second wires are alternately disposed in slit shapes over the entire first layer.

13. The semiconductor device according to claim 10 , wherein
the inductor is formed in a helical shape in the plan view and has a larger inner diameter than a predetermined inner diameter,
the wiring width of the first wiring located in a center region of the formation region of the inductor in the plan view among the plurality of first wires is formed wider than the wiring width of the first wiring located in a rest of the formation region of the inductor, and
a wiring width of the second wiring located in the center region of the formation region of the inductor in the plan view among the plurality of second wires is formed wider than a wiring width of the second wiring located in the rest of the formation region of the inductor.

14. The semiconductor device according to claim 10 , wherein
the inductor is formed in a helical shape in the plan view and has a smaller inner diameter than a predetermined inner diameter,
the plurality of first wires include a predetermined spatial region in the first layer located in a center region of the formation region of the inductor in the plan view, and
the plurality of second regions include a predetermined spatial region in the first layer located in the center region of the formation region of the inductor in the plan view.

15. The semiconductor device according to claim 1 , further comprising a plurality of third wires formed in a third layer stacked on the first layer, and configured to indicate a fixed potential,
wherein a wiring width of the third wiring located in the range of the formation region of the inductor in the plan view among the plurality of third wires is formed narrower than a wiring width of the third wiring located outside the range of the formation region of the inductor.

16. An electronic circuit comprising an inductor adopting a structure of the semiconductor device according to claim 1 .

17. A method for forming a semiconductor device comprising:
forming in a first layer a plurality of first wires configured to indicate a fixed potential; and
forming an inductor in a second layer stacked on the first layer,
wherein, in the forming the plurality of first wires, a wiring width of the first wire located within a range of a formation region of the inductor in a plan view among the plurality of first wires is narrowed compared to a wiring width of the first wire located outside the range of the formation region of the inductor.

18. A semiconductor device comprising:
a first wiring formed in a first layer and configured to indicate a fixed potential; and
an inductor formed in a second layer stacked on top of the first layer,
wherein a wiring width of the first wiring located within a range of a formation region of the inductor in a plan view among the plurality of first wires is formed narrower than a wiring width of the first wiring located outside the range of the formation region of the inductor.

19. The semiconductor device according to claim 18 , wherein the formation region of the inductor includes a region surrounded by an outer circumferential side of the inductor,
wherein a percentage per unit area that the first wiring occupy inside the inductor formation region is substantially the same as that occupied outside the inductor formation region.

Assignees

• Renesas Electronics Corp

Inventors

• Uchida Shinichi

Classifications

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/423

  Shielding layers · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/497 Primary

  Inductive arrangements or effects of, or between, wiring layers · CPC title