Circuits for and methods of implementing an inductor and a pattern ground shield in an integrated circuit

Patent metadata

Field	Value
Publication number	US-10217703-B2
Application number	US-201715397612-A
Country	US
Kind code	B2
Filing date	Jan 3, 2017
Priority date	Jan 3, 2017
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

An integrated circuit device is described. The integrated circuit device comprises a substrate; a plurality of metal routing interconnect layers; an inductor formed in at least one metal layer of the plurality of metal routing interconnect layers; and a bottom metal layer between the plurality of metal routing interconnect layers and the substrate; wherein a pattern ground shield is formed in the bottom metal layer. A method of implementing an integrated circuit device is also disclosed.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a substrate;
a plurality of metal routing interconnect layers;
an inductor formed in at least one metal layer of the plurality of metal routing interconnect layers; and
a bottom metal layer between the plurality of metal routing interconnect layers and the substrate;
wherein a pattern ground shield is formed in the bottom metal layer, the pattern ground shield comprising bottom metal traces in the bottom metal layer, a metal routing interconnect layer of the plurality of metal routing interconnect layers being over and adjacent the bottom metal layer, the metal routing interconnect layer comprising a first metal trace and a second metal trace, the first metal trace and the second metal trace being connected to alternating ones of the bottom metal traces by respective vias.

2. The integrated circuit device of claim 1 wherein the pattern ground shield is coupled to the substrate by way of a contact element between the bottom metal layer and the substrate.

3. The integrated circuit device of claim 2 wherein the contact element comprises a diffusion contact element formed on the substrate.

4. The integrated circuit device of claim 1 further comprising an isolation wall extending above the pattern ground shield and surrounding the inductor, wherein the isolation wall includes the first metal trace and the second metal trace.

5. The integrated circuit device of claim 4 wherein the isolation wall comprises a current return path for the inductor.

6. The integrated circuit device of claim 1 wherein the pattern ground shield is formed in either an M0 layer or an M1 layer.

7. The integrated circuit device of claim 1 wherein the plurality of metal routing interconnect layers comprises unidirectional metal layers.

8. The integrated circuit device of claim 1 wherein the bottom metal layer comprises a unidirectional metal layer.

9. The integrated circuit device of claim 1 wherein the inductor is formed in a plurality of metal layers comprising bi-directional metal layers.

10. The integrated circuit device of claim 1 wherein transistors of the integrated circuit device have gate widths that are less than 10 nanometers and the bottom metal layer has metal traces having trace widths that are approximately 20 nanometers.

11. An integrated circuit device, comprising:
a substrate;
a plurality of metal routing interconnect layers;
an inductor formed in at least one metal layer of the plurality of metal routing interconnect layers; and
an isolation wall extending above a pattern ground shield and surrounding the inductor;
wherein the pattern ground shield is formed in a bottom layer of the plurality of metal routing interconnect layers, and the bottom layer is a unidirectional metal layer and is connected to the isolation wall using a trace of a layer of the plurality of metal routing interconnect layers above the bottom layer.

12. The integrated circuit device of claim 11 wherein the pattern ground shield is coupled to the substrate by way of the trace of the layer of the plurality of metal routing interconnect layers.

13. The integrated circuit device of claim 12 wherein the isolation wall extends to the substrate.

14. The integrated circuit device of claim 13 wherein transistors of the integrated circuit device have gate widths that are less than 10 nanometers and the bottom layer has metal traces having trace widths that are approximately 20 nanometers.

15. The integrated circuit device of claim 11 wherein the inductor is formed in upper metal layers of the plurality of metal routing interconnect layers.

16. An integrated circuit device comprising:
a substrate; and
metal layers over the substrate; and
wherein:
an inductor is formed in an upper one or more of the metal layers;
a pattern ground shield is formed in a lower one of the metal layers, the pattern ground shield being formed of sets of unidirectional metal traces of the lower one of the metal layers; and
an isolation wall is formed in the metal layers and surrounding the inductor, the isolation wall comprising, for each of the sets of unidirectional traces, a first metal trace and a second metal trace in a mid-layer of the metal layers over the lower one of the metal layers, wherein for each of the sets of unidirectional traces, the first metal trace and the second metal trace are connected by vias to alternating ones of the unidirectional traces of the respective set of unidirectional traces.

17. The integrated circuit device of claim 16 , wherein the lower one of the metal layers is an M0 layer.

18. The integrated circuit device of claim 16 further comprising a contact element connecting the pattern ground shield to the substrate.

19. The integrated circuit device of claim 16 , wherein the upper one or more of the metal layers are bi-directional metal layers.

20. The integrated circuit device of claim 16 , wherein the isolation wall comprises a current return path for the inductor.

Assignees

• Xilinx Inc

Inventors

• Upadhyaya Parag
• Jing Jing

Classifications

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/423 Primary

  Shielding layers · CPC title