Bi-level adaptive equalizer

Patent metadata

Field	Value
Publication number	US-11038723-B2
Application number	US-202016778955-A
Country	US
Kind code	B2
Filing date	Jan 31, 2020
Priority date	Sep 10, 2019
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

At least some aspects of the present disclosure provide for a method. In at least one example, the method includes applying first equalization to a received data signal to generate an equalizer signal and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result. The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages. The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts and applying second equalization to the received data signal based on the determined relationship among the plurality of counts.

First claim

What is claimed is:

1. A circuit, comprising:
an equalizer comprising an input terminal configured to receive a data signal and an output terminal, wherein the equalizer is configured to receive an equalizer setting and generate an equalized signal according to the data signal and the equalizer setting;
a comparator comprising a first input terminal coupled to the output terminal of the equalizer, a second input terminal configured to receive a plurality of threshold signals, and an output terminal at which the comparator is configured to output a comparison result indicating a result of a comparison between the equalized signal and a respective threshold signal of the plurality of threshold signals under current consideration;
a counter comprising an input terminal and an output terminal and being configured to count a number of rising edges of the comparison result; and
a controller comprising an input terminal coupled to the output terminal of the comparator and an output terminal coupled to a control input of the equalizer, wherein the controller is configured to:
control the equalizer to apply a short conductor equalizer setting;
determine a relationship among counts output by the counter for multiple of the plurality of threshold signals; and
control the equalizer to remain at the short conductor equalizer setting or control the equalizer to apply a long conductor equalizer setting based on the determined relationship.

2. The circuit of claim 1 , further comprising a divider coupled between the output terminal of the comparator and the input terminal of the counter, wherein the divider is configured to divide a frequency of the comparison result prior to counting of the rising edges of the comparison result by the counter.

3. The circuit of claim 1 , further comprising a digital-to-analog converter (DAC) having an input terminal coupled to a second output terminal of the controller and an output terminal coupled to the second input terminal of the comparator, wherein the DAC is configured to receive a plurality of threshold values from the controller and generate the plurality of threshold signals based on the plurality of threshold values.

4. The circuit of claim 1 , wherein determining the relationship among the counts output by the counter comprises determining that a conductor over which the data signal is received is a short conductor when at least three counts output by the counter and corresponding to three separate threshold signals of the plurality of threshold signals are approximately equal in value.

5. The circuit of claim 1 , wherein determining the relationship among the counts output by the counter comprises determining that a conductor over which the data signal is received is a long conductor when at a first count output by the counter corresponding to a first of three separate threshold signals of the plurality of threshold signals or a second count output by the counter corresponding to a second of the three separate threshold signals has a value outside a predetermined allowable variance from a value of a third count output by the counter corresponding to a third of the three separate threshold signals.

6. The circuit of claim 5 , wherein the first of the three separate threshold signals varies from the third of the three separate threshold signals by X units, and wherein the second of the three separate threshold signals varies from the third of the three threshold signals by X+1 units, X is a non-zero positive integer.

7. The circuit of claim 5 , wherein controlling the equalizer to apply the short equalizer setting or the long equalizer setting is performed without performing clock data recovery on the data signal.

8. A system, comprising:
a processor;
a non-transitory memory; and
an equalization adaptation computer program product stored in the non-transitory memory that, when executed by the processor, causes the processor to:
control an equalizer to apply first equalization to a received data signal to generate an equalized signal;
control a digital-to-analog converter (DAC) to output a plurality of threshold signals for comparison to the equalized signal;
determine a count of rising edges in a comparison result of the comparison of the equalized signal to the threshold signal for a predetermined period of time for each of the plurality of threshold signals;
determine a relationship among multiple of the determined counts of rising edges; and

control the equalizer to apply second equalization to the received data signal according to the determined relationship;
wherein the processor is further configured to determine the relationship among multiple of the determined counts of rising edges by determining that a conductor over which the data signal is received is a short conductor when at least three of the determined counts of rising edges, each of which uniquely corresponding to one of three separate threshold signals of the plurality of threshold signals, are approximately equal in value.

9. The system of claim 8 , wherein the first equalization is equalization for the short conductor and controlling the equalizer to apply second equalization to the received data signal according to the determined relationship comprises controlling the equalizer to apply equalization for a long conductor.

10. A system, comprising:
a processor;
a non-transitory memory; and
an equalization adaptation computer program product stored in the non-transitory memory that, when executed by the processor, causes the processor to:
control an equalizer to apply first equalization to a received data signal to generate an equalized signal;
control a digital-to-analog converter (DAC) to output a plurality of threshold signals for comparison to the equalized signal;
determine a count of rising edges in a comparison result of the comparison of the equalized signal to the threshold signal for a predetermined period of time for each of the plurality of threshold signals;
determine a relationship among multiple of the determined counts of rising edges; and

control the equalizer to apply second equalization to the received data signal according to the determined relationship;
wherein the processor is further configured to determine the relationship among multiple of the determined counts of rising edges by determining that a conductor over which the data signal is received is a long conductor when a first of the determined counts of rising edges, corresponding to a first of three separate threshold signals of the plurality of threshold signals, or a second of the determined counts of rising edges, corresponding to a second of the three separate threshold signals, has a value outside a predetermined allowable variance from a value of a third of the determined counts of rising edges, corresponding to a third of the three separate threshold signals.

11. The system of claim 10 , wherein the first of the three separate threshold signals varies from the third of the three separate threshold signals by X units, and wherein the second of the three separate threshold signals varies from the third of the three threshold signals by X+1 units, X is a non-zero positive integer.

12. The system of claim 10 , wherein the first equalization is equalization for a short conductor and controlling the equalizer to apply second equalization to the received data signal according to the determined relationship comprises maintaining the equalization for the short conductor unchanged.

13. A method, comprising:
applying first equalization to a received data signal to generate an equalized signal;
comparing the equalized signal to each of a plurality of reference v

Assignees

• Texas Instruments Inc

Inventors

• Rane Amit
• Campbell Charles Michael
• Vining Suzanne Mary

Classifications

• H04L2025/03745

  Timing of adaptation · CPC title

• G11B20/10222

  clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation (dedicated sync patterns in the modulation code G11B20/1403) · CPC title

• G11B20/10046

  filtering or equalising, e.g. setting the tap weights of an FIR filter · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title