Bonded die assembly containing partially filled through-substrate via structures and methods for making the same

Patent metadata

Field	Value
Publication number	US-11037908-B2
Application number	US-201916521849-A
Country	US
Kind code	B2
Filing date	Jul 25, 2019
Priority date	Jul 25, 2019
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion. The bonded assembly includes a second semiconductor die attached to the first semiconductor die, and including a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect structures, and bonding pad structures electrically connected to a respective one of the second metal interconnect structures and bonded to a respective first through-substrate via structure.

First claim

The invention claimed is:

1. A bonded assembly comprising:
a first semiconductor die comprising a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and the first semiconductor devices and contacting a respective one of the first metal interconnect structures, wherein each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion; and
a second semiconductor die attached to the first semiconductor die, and comprising a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect structures, and bonding pad structures electrically connected to a respective one of the second metal interconnect structures and bonded to a respective one of the first through-substrate via structures;
wherein:
the first semiconductor die comprises a memory die and the first semiconductor devices include a three-dimensional array of memory elements; and
the second semiconductor die comprises a logic die including a peripheral circuitry configured to control operation of the three-dimensional array of memory elements.

2. The bonded assembly of claim 1 , wherein:
the first semiconductor die comprises a backside insulating layer contacting a backside surface of the first substrate; and
each of the first through-substrate via structures contacts a horizontal surface of the backside insulating layer.

3. The bonded assembly of claim 2 , wherein each of the first through-substrate via structures comprises a respective metallic liner contacting a horizontal surface of a respective one of the first metal interconnect structures and an annular portion of the horizontal surface of the backside insulating layer.

4. The bonded assembly of claim 3 , wherein each of the first through-substrate via structures further comprises a respective metal layer consisting essentially of at least one elemental metal and laterally enclosing the void or the dielectric fill material portion.

5. The bonded assembly of claim 4 , wherein the respective metal layer consists essentially of copper and contacts an inner sidewall of the metallic liner.

6. The bonded assembly of claim 1 , wherein each of the bonding pad structures is bonded to the respective one of the first through-substrate via structures through a respective solder material portion.

7. The bonded assembly of claim 1 , wherein each of the bonding pad structure is bonded to the respective one of the first through-substrate via structures by metal-to-metal bonding.

8. The bonded assembly of claim 1 , further comprising cylindrical insulating spacers vertically extending through at least the first substrate, wherein each of the first through-substrate via structures extends through, and contacts an inner sidewall of, a respective one of the cylindrical insulating spacers.

9. The bonded assembly of claim 8 , wherein the respective one of the first metal interconnect structures is in contact with an annular bottom surface of a respective one of the cylindrical insulating spacers.

10. The bonded assembly of claim 1 , further comprising a third semiconductor die attached to the first semiconductor die, and comprising a third substrate, third semiconductor devices located on the third substrate, third dielectric material layers located on the third semiconductor devices and embedding third metal interconnect structures, and additional through-substrate via structures extending through the third substrate and electrically connected to a respective one of the third metal interconnect structures and bonded to a respective one of additional bonding pad structures within the first semiconductor die.

11. The bonded assembly of claim 1 , wherein the first semiconductor devices comprise a dielectric material portion around the three-dimensional array of memory elements, and at least one of the first through-substrate via structures extends through the dielectric material portion around the three-dimensional array of memory elements.

12. The bonded assembly of claim 1 , wherein at least one of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void.

13. A bonded assembly comprising:
a first semiconductor die comprising a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and the first semiconductor devices and contacting a respective one of the first metal interconnect structures, wherein each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion;
a second semiconductor die attached to the first semiconductor die, and comprising a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect structures, and bonding pad structures electrically connected to a respective one of the second metal interconnect structures and bonded to a respective one of the first through-substrate via structures; and
a third semiconductor die attached to the first semiconductor die, and comprising a third substrate, third semiconductor devices located on the third substrate, third dielectric material layers located on the third semiconductor devices and embedding third metal interconnect structures, and additional through-substrate via structures extending through the third substrate and the third semiconductor devices and electrically connected to a respective one of the third metal interconnect structures and bonded to a respective one of additional bonding pad structures within the first semiconductor die, wherein each of the each of the additional through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion, and wherein:
at least one of the first semiconductor die and the third semiconductor die comprises a memory die and at least one of the first semiconductor devices and the third semiconductor devices comprise a three-dimensional array of memory elements.

14. The bonded assembly of claim 13 , wherein at least one of the first semiconductor devices and the third semiconductor devices comprise a dielectric portion around a three-dimensional array of memory elements, and the at least one through-substrate via structure laterally surrounding the core cavity that contains the void or the dielectric fill material portion extends through the dielectric material portion around the three-dimensional array of memory elements.

15. The bonded assembly of claim 13 , wherein at least one of the through-substrate via structures laterally surrounds a respective core cavity that contains the void.

Assignees

• Sandisk Technologies Llc

Inventors

• Wu Chen
• Rabkin Peter
• Chen Yangyin
• Higashitani Masaaki

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title