Transistor device with sinker contacts and methods for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11037816-B2
Application number	US-201715649774-A
Country	US
Kind code	B2
Filing date	Jul 14, 2017
Priority date	Mar 13, 2017
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

In described examples, a device includes a semiconductor substrate; a buried layer; and a trench with inner walls extending from the buried layer to a surface of the semiconductor substrate, the trench having sidewalls, a bottom wall, a barrier layer including a titanium (Ti) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material formed on the barrier layer.

First claim

What is claimed is:

1. A device, comprising:
a semiconductor substrate;
a buried layer; and
a trench with inner walls extending from the buried layer to a surface of the semiconductor substrate, the trench having sidewalls, a bottom wall, a barrier layer including a titanium (Ti) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material formed on the barrier layer.

2. The device of claim 1 , in which the more than one layer of conductor material includes a first chemical vapor deposited tungsten (CVD-W) layer, and a second CVD-W layer on the first CVD-W layer.

3. The device of claim 1 , in which the trench is filled with a first CVD-W layer, a second layer CVD-W layer, and a third CVD-W.

4. The device of claim 2 , in which a thickness of the more than one layer of conductor material of CVD-W is equal to or less than about 700 nm.

5. The device of claim 1 , in which the trench forms a sinker contact that is round and has a diameter greater than about 0.8 microns.

6. The device of claim 1 , in which the barrier layer includes a titanium nitride (TiN) layer above the Ti layer.

7. The device of claim 6 in which the TiN layer includes a portion positioned at an opening of the trench at the substrate surface.

8. The device of claim 1 , in which the buried layer includes an n-type drain region of a vertical NMOS transistor.

9. The device of claim 1 , in which the buried layer includes an n-type collector region of a vertical NPN bipolar transistor.

10. The device of claim 1 , in which the buried layer is p-type and is a drain of a vertical PMOS transistor.

11. The device of claim 1 , in which the buried layer is p-type and is a collector of a vertical PNP bipolar transistor.

12. A device, comprising:
a semiconductor substrate;
a buried layer of a first conductivity type;
a first region of the first conductivity type over the buried layer;
a second region of a second conductivity type in the first region;
a third region of the first conductivity type at a surface of the second region;
a gate trench extending through the second region;
a source contact to the third region; and
a trench with walls extending from the buried layer to a surface of the semiconductor substrate, the trench having sidewalls, a bottom wall, a barrier layer including a titanium nitride (TiN) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material formed on the barrier layer.

13. The device of claim 12 , wherein the more than one layer of conductor material includes a first tungsten layer and a second tungsten layer on the first tungsten layer.

14. The device of claim 12 , wherein the trench is filled with a first tungsten layer, a second layer tungsten layer, and a third tungsten layer.

15. The device of claim 12 , wherein the trench forms a sinker contact that is round and has a diameter greater than about 0.8 microns.

16. The device of claim 12 , wherein the barrier layer includes a titanium (Ti) layer under the TiN layer.

17. The device of claim 16 , wherein a portion of the Ti layer at an opening of the trench at the substrate surface is converted to TiN.

Assignees

• Texas Instruments Inc

Inventors

• Yang Hong
• Chisholm Michael F
• Xiong Yufei
• Liu Yunlong

Classifications

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/0148 Primary

  comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers · CPC title

• H10W10/17 Primary

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• C23C16/306

  AII BVI compounds, where A is Zn, Cd or Hg and B is S, Se or Te · CPC title

• H01L21/76232

  Electricity · mapped topic