Low resistance sinker contact

Patent metadata

Field	Value
Publication number	US-9397180-B1
Application number	US-201514695290-A
Country	US
Kind code	B1
Filing date	Apr 24, 2015
Priority date	Apr 24, 2015
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising the steps:
providing substrate with a transistor covered by a pre-metal dielectric layer;
forming a contact pattern on the pre-metal dielectric layer with openings where contacts are to be formed;
etching contact openings through the pre-metal dielectric and forming a contact opening to a first node of the transistor;
removing the contact pattern;
forming a sinker contact pattern on the pre-metal dielectric layer with an opening where the low resistance sinker contact is to be formed;
etching a sinker contact through the pre-metal dielectric and etching the sinker contact through a first doped layer and into a second doped layer wherein the first doped layer and the second doped layer have the same doping type and wherein the second doped layer is more heavily doped than the first doped layer and wherein the first doped layer and the second doped layer form a second node of the transistor;
removing the sinker contact pattern;
depositing a barrier layer into the contact openings and into the low resistance sinker contact opening;
depositing a metallic material into and filling the contact openings and into and filling the low resistance sinker contact opening; and
removing metallic material overfill to form contact plugs and to form a low resistance sinker contact plug.

2. The method of claim 1 , further including implanting dopant into the sidewalls and into the bottom of the low resistance sinker contact prior to removing the sinker contact pattern and forming a low resistance highly doped diffusion on the sidewalls and bottom of the low resistance sinker contact.

3. The method of claim 1 , wherein the transistor is a high power MOS transistor and the low resistance sinker contact is coupled between interconnect and the highly doped buried layer under the high power MOS transistor.

4. The method of claim 3 , wherein the heavily doped buried layer is the source of a bidirectional high power MOS transistor.

5. The method of claim 3 , wherein the heavily doped buried layer is the drain of a unidirectional high power MOS transistor.

6. The method of claim 3 , wherein the heavily doped buried layer is the collector of a high power vertical bipolar transistor.

7. The method of claim 1 , wherein the barrier layer is titanium plus titanium nitride and where the metallic material is CVD-W.

8. The method of claim 1 , wherein the barrier layer is tantalum plus a copper seed and the metallic material is electroplated copper.

9. The method of claim 1 , wherein the low resistance sinker contact is etched into the substrate between 0.5 um and 5 um.

10. The method of claim 1 wherein the steps of forming a sinker contact pattern, etching a sinker contact, and removing the sinker contact pattern are performed prior to the step of forming a contact pattern.

11. The method of claim 1 , wherein the step of etching the sinker contact further includes etching the sinker contact through the isolation dielectric.

Assignees

• Texas Instruments Inc

Inventors

• Yang Hong
• Sridhar Seetharaman
• Xiong Yufei
• Liu Yunlong
• Lee Zachary K
• Hu Peng

Classifications

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title