Method for III-V/silicon hybrid integration

Patent metadata

Field	Value
Publication number	US-11036005-B2
Application number	US-201916532406-A
Country	US
Kind code	B2
Filing date	Aug 5, 2019
Priority date	Aug 6, 2018
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

A method of transfer printing. The method comprising: providing a precursor photonic device, comprising a substrate and a bonding region, wherein the precursor photonic device includes one or more alignment marks located in or adjacent to the bonding region; providing a transfer die, said transfer die including one or more alignment marks; aligning the one or more alignment marks of the precursor photonic device with the one or more alignment marks of the transfer die; and bonding at least a part of the transfer die to the bonding region.

First claim

The invention claimed is:

1. A method of transfer printing, comprising:
providing a precursor photonic device, comprising a substrate having a cavity and a bonding region, wherein the precursor photonic device includes one or more alignment marks located in or adjacent to the bonding region in a bed of the cavity;
providing a transfer die, said transfer die including one or more alignment marks in an optically transparent region of the transfer die;
aligning the one or more alignment marks of the precursor photonic device with the one or more alignment marks of the transfer die; and
bonding at least a part of the transfer die to the bonding region.

2. The method of claim 1 , further comprising a step of filling a facet between the precursor photonic device and the transfer die.

3. The method of claim 2 , wherein a filling material used to fill the facet is either of silicon nitride or amorphous silicon.

4. The method of claim 1 , further comprising one or more steps of:
plasma treating the precursor photonic device and/or the transfer die;
dipping the precursor photonic device in water;
drying the precursor photonic device; and
annealing the transfer die and precursor photonic device.

5. The method of claim 4 , wherein the annealing is performed at a temperature of at least 250° C. and no more than 350° C. for a time of at least 20 minutes and no more than 40 minutes.

6. The method of claim 5 , wherein the annealing is performed in an inert gas atmosphere including nitrogen or argon.

7. An optoelectronic device, comprising:
a silicon-on-insulator wafer, having a cavity and one or more alignment marks in a bed of the cavity; and
a III-V semiconductor based photonic device, located within and bonded to the cavity,
wherein the III-V semiconductor based photonic device includes one or more corresponding alignment marks in an optically transparent region of the III-V semiconductor based photonic device, which overlap with the one or more alignment mark(s) in the bed of the cavity.

8. The optoelectronic device of claim 7 , wherein the one or more corresponding alignment marks of the III-V semiconductor based photonic device are voids in the III-V semiconductor based photonic device that extend entirely through the III-V semiconductor based photonic device.

9. The optoelectronic device of claim 7 , further comprising an input and/or output waveguide, the waveguide(s) being provided in the silicon-on-insulator wafer and optically coupled to the III-V semiconductor based photonic device.

10. A precursor photonic device, comprising:
a substrate having a cavity;
a bonding region, for receiving and bonding to a transfer die; and
one or more optical alignment marks, for use in transfer printing, said optical alignment marks being located in or adjacent to the bonding region in a bed of the cavity.

11. The precursor photonic device of claim 10 , wherein the one or more optical alignment marks are provided as one or more etched regions and/or as one or more patterned metal surfaces.

12. A method of preparing the precursor photonic device of claim 10 , comprising the steps of:
providing a wafer, comprising a substrate and a device layer; and
etching one or more optical alignment marks into the wafer.

13. The method of claim 12 , the method further comprising:
etching a cavity into the wafer; and
a step of etching at least one of an input waveguide and an output waveguide, said input waveguide and/or output waveguide having a surface adjacent to the cavity.

14. The method of claim 13 , wherein the step of etching the one or more optical alignment marks is performed at the same time as etching the input waveguide and/or output waveguide.

15. The method of claim 12 , further comprising:
etching a cavity into the wafer; and
a step of depositing an antireflective coating, along either or both of: one or more sidewalls; and/or a bed of the cavity.

16. The method of claim 15 , wherein the antireflective coating is formed of silicon nitride.

17. The method of claim 15 , further comprising a step of removing at least the antireflective coating present adjacent to the optical alignment marks.

18. The precursor photonic device of claim 10 , wherein an alignment mark of the one or more optical alignment marks extends further into the substrate than the bed of the cavity.

19. The precursor photonic device of claim 10 , wherein an alignment mark of the one or more optical alignment marks projects in at least two non-parallel directions.

20. The precursor photonic device of claim 10 , wherein an alignment mark of the one or more optical alignment marks includes a coarse alignment mark and a fine alignment mark.

Assignees

• Rockley Photonics Ltd

Inventors

• Yu Guomin
• Zilkie Aaron John

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title