Interconnection structures and methods for transfer-printed integrated circuit elements with improved interconnection alignment tolerance

Patent metadata

Field	Value
Publication number	US-9899329-B2
Application number	US-201113302497-A
Country	US
Kind code	B2
Filing date	Nov 22, 2011
Priority date	Nov 23, 2010
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed.

First claim

That which is claimed:

1. A method of assembling integrated circuit elements on a substrate, the method comprising:
providing integrated circuit elements on a receiving substrate having pre-determined corresponding desired positions, each of the integrated circuit elements comprising a chiplet substrate including a connection pad and a conductor element on a surface thereof, wherein the connection pad and the conductor element are electrically separated, and wherein at least one of the integrated circuit elements is misaligned on the receiving substrate relative to the corresponding desired position thereon such that the at least one of the integrated circuit elements is positioned on the receiving substrate at a distance from the corresponding desired position that is greater than or equal to a distance between the conductor element and the connection pad; and
forming a conductive layer on the receiving substrate including the integrated circuit elements thereon such that the connection pad of each of the integrated circuit elements is electrically connected to the conductive layer and the conductor element is separated from the conductive layer notwithstanding that the at least one of the integrated circuit elements is misaligned on the receiving substrate.

2. The method of claim 1 , wherein each of the integrated circuit elements includes an insulating layer on the chiplet substrate that exposes at least a portion of the connection pad to the conductive layer and covers the conductor element on the surface of each chiplet substrate to electrically separate the conductor element from the conductive layer.

3. The method of claim 2 , wherein forming the conductive layer comprises:
forming a planarization layer including via openings therein on the receiving substrate including the integrated circuit elements thereon, wherein respective positions of the via openings in the planarization layer are based on respective desired positions of the integrated circuit elements on the receiving substrate; and then
forming the conductive layer on the planarization layer and in the via openings to electrically contact the connection pad of each of the integrated circuit elements.

4. The method of claim 2 , wherein providing the integrated circuit elements on the receiving substrate comprises:
forming the integrated circuit elements including a plurality of active elements on a source substrate; and
transferring the integrated circuit elements from the source substrate to the receiving substrate such that the at least one of the integrated circuit elements is misaligned on the receiving substrate relative to the desired position.

5. The method of claim 2 , wherein the connection pad of each of the integrated circuit elements is coupled to an active element therein such that the conductive layer provides an electrical connection between respective active elements of each chiplet substrate, and wherein the conductor element of each of the integrated circuit elements provides an electrical connection between respective active elements of a same chiplet substrate.

6. A method of assembling integrated circuit elements on a substrate, the method comprising:
providing integrated circuit elements on a receiving substrate, each of the integrated circuit elements comprising a chiplet substrate including a connection pad and a conductor element on a surface thereof, wherein the connection pad and the conductor element are electrically separated, and wherein at least one of the integrated circuit elements is misaligned on the receiving substrate relative to a desired position thereon such that the at least one of the integrated circuit elements is positioned on the receiving substrate at a distance from the desired position that is greater than or equal to a distance between the conductor element and the connection pad; and
forming a conductive layer on the receiving substrate including the integrated circuit elements thereon such that the connection pad of each of the integrated circuit elements is electrically connected to the conductive layer notwithstanding that the at least one of the integrated circuit elements is misaligned on the receiving substrate,
wherein each of the integrated circuit elements includes an insulating layer on the chiplet substrate that exposes at least a portion of the connection pad to the conductive layer and covers the conductor element on the surface of each chiplet substrate to electrically separate the conductor element from the conductive layer,
wherein forming the conductive layer comprises:
forming a planarization layer including via openings therein on the receiving substrate including the integrated circuit elements thereon, wherein respective positions of the via openings in the planarization layer are based on respective desired positions of the integrated circuit elements on the receiving substrate; and then
forming the conductive layer on the planarization layer and in the via openings to electrically contact the connection pad of each of the integrated circuit elements, and

wherein at least one of the via openings exposes a portion of the connection pad and a portion of the insulating layer covering the conductor element of the at least one of the integrated circuit elements that is misaligned on the receiving substrate.

7. The method of claim 6 , wherein the exposed portion of the connection pad is smaller than a dimension of the at least one via opening.

8. A method of assembling integrated circuit elements on a substrate, the method comprising:
providing integrated circuit elements on a receiving substrate, each of the integrated circuit elements comprising a chiplet substrate including a connection pad and a conductor element on a surface thereof, wherein the connection pad and the conductor element are electrically separated, and wherein at least one of the integrated circuit elements is misaligned on the receiving substrate relative to a desired position thereon such that the at least one of the integrated circuit elements is positioned on the receiving substrate at a distance from the desired position that is greater than or equal to a distance between the conductor element and the connection pad; and
forming a conductive layer on the receiving substrate including the integrated circuit elements thereon such that the connection pad of each of the integrated circuit elements is electrically connected to the conductive layer notwithstanding that the at least one of the integrated circuit elements is misaligned on the receiving substrate,
wherein each of the integrated circuit elements includes an insulating layer on the chiplet substrate that exposes at least a portion of the connection pad to the conductive layer and covers the conductor element on the surface of each chiplet substrate to electrically separate the conductor element from the conductive layer,
wherein the connection pad of each of the integrated circuit elements is coupled to an active element therein such that the conductive layer provides an electrical connection between respective active elements of each chiplet substrate, and wherein the conductor element of each of the integrated circuit elements provides an electrical connection between respective active elements of a same chiplet substrate, and
wherein each chiplet substrate includes a plurality of connection pads and a plurality of conductor elements, and wherein at least one of the conductor elements is provided between adjacent ones of the connection pads on the surface of each chiplet substrate.

9. A method of assembling integrated circuit elements on a substrate, the method comprising:
providing integrated circuit elements on a receiving substrate, each of the integrated circuit e

Assignees

• Bower Christopher
• X Celeprint Ltd

Inventors

• Bower Christopher

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W72/07131

  Means for applying material, e.g. for deposition or forming coatings · CPC title