Serdes pre-equalizer having adaptable preset coefficient registers

Patent metadata

Field	Value
Publication number	US-11032111-B2
Application number	US-201916552927-A
Country	US
Kind code	B2
Filing date	Aug 27, 2019
Priority date	Aug 28, 2018
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

An illustrative SerDes (serializer-deserializer) communications method embodiment may include a transceiver: selecting one of multiple registers to specify initial pre-equalizer coefficient values; updating the initial pre-equalizer coefficient values during a training phase; and using the updated pre-equalizer coefficient values to convey a transmit data stream. In an illustrative embodiment of a chip-to-module communications link, a port connector couples a port transceiver to a pluggable module transceiver, the pluggable module transceiver including: one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.

First claim

What is claimed is:

1. A SerDes communications method that comprises, in a transceiver:
selecting one of multiple registers to specify initial pre-equalizer coefficient values, each of the multiple registers corresponding to a different channel model;
updating the initial pre-equalizer coefficient values during a training phase; and
using the updated pre-equalizer coefficient values to convey a transmit data stream.

2. The method of claim 1 , wherein at least some of the different channel models are for chip-to-module (C2M) channels with different insertion loss and package loss characteristics.

3. The method of claim 1 , wherein at least some of the different channel models presume different types of receiver equalization.

4. The method of claim 1 , wherein said selecting includes using the initial pre-equalizer coefficient values to determine a performance characteristic for each of the multiple registers.

5. The method of claim 4 , wherein the performance characteristic is an error signal energy.

6. The method of claim 4 , wherein the performance characteristic is a bit error rate.

7. The method of claim 4 , further comprising updating the selected register with the updated pre-equalizer coefficient values.

8. A chip-to-module communications link that comprises a port connector coupling a port transceiver to a pluggable module transceiver, the pluggable module transceiver including:
one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and
a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values corresponding to a different channel model, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.

9. The communications link of claim 8 , wherein at least some of the different channel models are for chip-to-module (C2M) channels with different insertion loss and package loss characteristics.

10. The communications link of claim 8 , wherein at least some of the different channel models presume different types of receiver equalization.

11. A chip-to-module communications link that comprises a port connector coupling a port transceiver to a pluggable module transceiver, the pluggable module transceiver including:
one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and
a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values for which the port transceiver determines a performance characteristic,
the controller using one of the registers selected by the port transceiver to specify the initial coefficient values for the one or more transmit filters.

12. The communications link of claim 11 , wherein the performance characteristic is an error signal energy.

13. The communications link of claim 11 , wherein the performance characteristic is a bit error rate.

14. The communications link of claim 11 , wherein the port transceiver generates updates for the coefficient values of the one or more transmit filters.

15. The communications link of claim 14 , wherein the controller saves updated coefficient values in one of the registers.

16. A pluggable module transceiver including:
one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to a port transceiver; and
a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values corresponding to a different channel model, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.

17. The pluggable module transceiver of claim 16 , wherein the port transceiver determines a performance characteristic for each register.

18. The pluggable module transceiver of claim 17 , wherein the performance characteristic is an error signal energy.

19. The pluggable module transceiver of claim 17 , wherein the performance characteristic is a bit error rate.

Assignees

• Credo Tech Group Ltd

Inventors

• Sun Junqing
• Qian Haoli

Classifications

• H04L2025/03808

  Transmission of equaliser coefficients · CPC title

• H04L25/4904

  using self-synchronising codes, e.g. split-phase codes · CPC title

• H04L25/03019 Primary

  adaptive, i.e. capable of adjustment during data reception · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04B1/40

  Circuits · CPC title