Bidirectional switch having back to back field effect transistors

Patent metadata

Field	Value
Publication number	US-11031390-B2
Application number	US-201916560825-A
Country	US
Kind code	B2
Filing date	Sep 4, 2019
Priority date	Jun 30, 2016
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A bi-directional semiconductor switching device is formed by forming first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second. FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET.

First claim

What is claimed is:

1. A method for forming a bi-directional semiconductor switching device, comprising:
forming first and second vertical field effect transistors (FETs) in tandem from a semiconductor substrate, wherein a source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side, wherein gates for both the first and second FETs are disposed in tandem in a common set of trenches formed in a drift region of the semiconductor substrate that is sandwiched between the source for the first FET and the source for the second FET, wherein the drift region forms a common drain for both the first FET and the second FET wherein the drift region is of a same conductivity type as the source for the first FET and the source for the second FET but at a lower carrier concentration than that of the source for the first FET and the source for the second FET.

2. The method of claim 1 , wherein forming the first and second FETs comprises forming a set of trenches from the first side of the substrate into the drift region; implanting dopants of the same conductivity type as a substrate layer into bottoms of at least some of the trenches in the set;
forming a gate insulator on sidewalls and bottoms of the at least some of the trenches in the set;
forming gate electrodes for the second FET in lower portions of the trenches;
forming inter-gate dielectric over the gate electrodes for the second FET;
forming gate electrodes for the first FET in upper portions of the trenches above the inter-gate dielectric, wherein the gate electrodes of the first FET are electrically isolated from the sidewalls of the at least some of the trenches.

3. The method of claim 2 , wherein the first FET is a metal oxide semiconductor FET (MOSFET).

4. The method of claim 3 , further comprising implanting body dopants of a conductivity type opposite a conductivity type of the drift region into upper portions of the drift region proximate the gate electrodes for the first FET and diffusing the dopants to form a body region for the MOSFET.

5. The method of claim 4 , further comprising implanting source dopants of a same conductivity type as the drift region into upper portions of the drift region proximate the gate electrodes for the MOSFET and diffusing the source dopants to form source region for the MOSFET, wherein the body region for the MOSFET is between the source region for the MOSFET and the drift region.

6. The method of claim 3 , wherein the first FET is a first MOSFET and the second FET is a second MOSFET, wherein the substrate includes a substrate layer of a first conductivity type and a doped layer of a second conductivity type sandwiched between the drift region and the substrate layer, wherein the second conductivity type is opposite the first conductivity type, wherein the doped layer of the second conductivity type forms a body region for the second MOSFET, wherein the drift region is of a lesser doping concentration than the substrate layer.

7. The method of claim 6 , wherein forming the set of trenches includes forming the set of trenches to a depth sufficient for the trenches to penetrate into the body region for the second MOSFET but not into the substrate layer, the method further comprising implanting source dopants of the first conductivity type into portions of the body region for the second MOSFET at bottoms of the trenches before forming the gate electrodes and diffusing the source dopants to form source regions for the second MOSFET, wherein the source regions for the second MOSFET merge with the substrate layer.

8. The method of claim 3 , wherein the second FET is an accumulation mode FET (ACCUFET), wherein the substrate includes a substrate layer of a first conductivity type and the drift region is formed on the substrate layer, wherein the drift region is of the first conductivity type but of a lesser doping concentration than a doping concentration of the substrate layer.

9. The method of claim 8 , further comprising implanting counter dopants of the second conductivity type into portions of the drift region at bottoms of the trenches before forming the gate electrodes in the at least some of the trenches and diffusing the counter dopants to form well regions.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Lui Sik

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/0133

  Manufacturing common source or drain regions between multiple IGFETs · CPC title

• H10D84/131

  Thyristors having built-in components · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title