Method of fabricating packaging substrate

Patent metadata

Field	Value
Publication number	US-11031329-B2
Application number	US-201815961973-A
Country	US
Kind code	B2
Filing date	Apr 25, 2018
Priority date	May 23, 2016
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A method of fabricating a packaging substrate is provided, which includes: forming on a carrier a conductor layer having a plurality of openings; forming a plurality of conductive bumps on the conductor layer, wherein each of the conductive bumps has a post body disposed in a corresponding one of the openings and a conductive pad disposed on the conductor layer, the post body being integrally formed with the conductive pad and less in width than the conductive pad; forming a plurality of conductive posts on the conductive pads; forming on the carrier a first insulating layer that encapsulates the conductive bumps and the conductive posts; removing the carrier; and removing the entire conductor layer to expose the post bodies from a first surface of the first insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps.

First claim

What is claimed is:

1. A method for fabricating a packaging substrate, comprising:
forming on a carrier a conductor layer having a plurality of openings;
disposing a plurality of conductive bumps on the conductor layer, wherein each of the conductive bumps has a post body formed in a corresponding one of the openings and a conductive pad disposed on the conductor layer, the post body being integrally formed with and less in width than the conductive pad;
disposing a plurality of conductive posts on the conductive pads;
forming on the carrier a first insulating layer encapsulating the conductive bumps and the conductive posts;
removing the carrier; and
removing entirety of the conductor layer to expose the post bodies from a first surface of the first insulating layer.

2. The method of claim 1 , wherein the post bodies protrude from the first surface of the first insulating layer.

3. The method of claim 1 , further comprising, after removing the entirety of the conductor layer, forming at a position corresponding to the conductor layer a recessed portion with the post bodies of the conductive bumps protruding from a bottom surface of the recessed portion.

4. The method of claim 1 , further comprising, prior to forming the plurality of conductive bumps on the conductor layer, forming a first barrier layer on the conductor layer and in the openings.

5. The method of claim 4 , further comprising forming the first barrier layer on the carrier.

6. The method of claim 5 , further comprising, after removing the entirety of the conductor layer, removing entirety of the first barrier layer.

7. The method of claim 4 , further comprising forming a second barrier layer on the first barrier layer.

8. The method of claim 7 , further comprising, after removing the entirety of the conductor layer, removing entirety of the first barrier layer and entirety of the second barrier layer.

9. The method of claim 4 , wherein the first barrier layer is formed only between the conductive bumps and the conductor layer.

10. The method of claim 9 , wherein, after removing the entirety of the conductor layer, the first barrier layer is exposed from the first surface of the first insulating layer.

11. The method of claim 1 , further comprising disposing on the carrier a first circuit structure encapsulated by the first insulating layer.

12. The method of claim 1 , further comprising disposing a second circuit structure on the first insulating layer.

13. The method of claim 12 , further comprising forming on the first insulating layer a second insulating layer encapsulating the second circuit structure with a portion of the second circuit structure exposed from the second insulating layer.

Assignees

• Phoenix & Corp
• Phoenix Pioneer Technology Co Ltd

Inventors

• Hu Chu-Chin
• Hsu Shih-Ping
• Hsu Che-Wei
• Liu Chin-Ming
• Yang Chih-Kuai

Classifications

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title