Resistance variable memory device

Patent metadata

Field	Value
Publication number	US-11031077-B2
Application number	US-201916715343-A
Country	US
Kind code	B2
Filing date	Dec 16, 2019
Priority date	Apr 11, 2019
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A resistance variable memory device may include a plurality of memory cells and a control circuit block. The memory cells may be connected between a global word line and a global bit line. The control circuit block may control the memory cells. The control circuit block may include a write pulse control block. The write pulse control block may include a high resistance path circuit and a bypass circuit connected between the global word line and a selected memory cell. The write pulse control block may selectively enable any one of the high resistance path circuit and the bypass circuit in accordance with a position the selected memory cell.

First claim

What is claimed is:

1. A resistance variable memory device comprising:
a plurality of memory cells electrically coupled between a global word line and a global bit line; and
a control circuit block for controlling the plurality of memory cells,
wherein the control circuit block comprises a write pulse control block electrically coupled between the global word line and a selected memory cell among the plurality of memory cells to control a current flowing through the selected memory cell in accordance with a distance between the selected memory cell and the control circuit block, and
wherein the write pulse control block comprises:

a high resistance path circuit; and
a bypass circuit,
wherein any one of the high resistance path circuit and the bypass circuit is selectively connected between the global word line and the selected memory cell in accordance with the position of the selected memory cell.

2. The resistance variable memory device of claim 1 , wherein the high resistance path circuit is enabled when a memory cell among memory cells near to the control circuit block is turned-on, and the bypass circuit is enabled when a memory cell among memory cells far from the control circuit block is turned-on.

3. The resistance variable memory device of claim 1 , wherein the control circuit block comprises a detection circuit block configured to detect a turn-on of the selected memory cell based on the current of the selected memory cell and to generate a detection signal,
wherein the write pulse control block enables any one of the high resistance path circuit and the bypass circuit in response to the detection signal and address information of the selected memory cell.

4. The resistance variable memory device of claim 3 , wherein the control circuit block further comprises a control signal generation circuit for logically combining the detection signal provided form the detection circuit block with the address information of the selected memory cell to generate a control signal for enabling the high resistance path circuit and the bypass circuit of the write pulse control block.

5. The resistance variable memory device of claim 1 , wherein the write pulse control block comprises a high resistance path circuit and a bypass circuit connected between the global word line and the selected memory cell in parallel, the high resistance path circuit comprises a MOS transistor, and the MOS transistor of the high resistance path circuit has a resistance higher than a resistance of when the bypass circuit is selected and lower than a resistance of when the bypass circuit is not selected.

6. The resistance variable memory device of claim 1 , wherein the write pulse control block comprises a high resistance path circuit and a bypass circuit connected between the global word line and the selected memory cell in parallel, the high resistance path circuit comprises a variable resistance, and the variable resistance is higher than a resistance of when the bypass circuit is selected and lower than a resistance of when the bypass circuit is not selected.

7. The resistance variable memory device of claim 1 , wherein the write pulse control block comprises a high resistance path circuit and a bypass circuit connected between the global word line and the selected memory cell in parallel, and the high resistance path circuit comprises a plurality of parallelly connected transistors selected in response to a plurality of current control signals.

8. The resistance variable memory device of claim 1 , wherein the bypass circuit comprises a transfer gate including an NMOS transistor and a PMOS transistor.

9. The resistance variable memory device of claim 1 , further comprising a voltage control circuit electrically coupled with the global bit line, wherein the voltage control circuit provides the selected memory cell with an initial voltage for maintaining a turn-on of the selected memory cell when the selected memory cell is not turned-on, and the voltage control circuit provides the selected memory cell with a write voltage when the selected memory cell is turned-on.

10. The resistance variable memory device of claim 1 , further comprising a current control circuit electrically coupled with the global word line, wherein the current control circuit provides the selected memory cell with an initial current for maintaining a turn-on of the selected memory cell when the selected memory cell is not turned-on, and the current control circuit provides the selected memory cell with a write current when the selected memory cell is turned-on.

11. A resistance variable memory device comprising:
a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged between the word lines and the bit lines; and
a control circuit block arranged at an edge portion of the memory cell array to control the memory cells,
wherein the control circuit block comprises:
a detection circuit block configured to detect a turn-on of a selected memory cell among the plurality of memory cells to generate a detection signal in accordance with detection results, and
a write pulse control block configured to selectively connect a word line among the plurality of word lines connected the selected memory cell with a high resistance path circuit and a bypass circuit in accordance with the detection signal and address information of the selected memory cell.

12. The resistance variable memory device of claim 11 , wherein the write pulse control block is configured to enable the high resistance path circuit when the detection signal is enabled and the address of the selected memory cell is within a near cell group arranged near to the control circuit block, and the write pulse control block is configured to enable the bypass circuit when the detection signal is not enabled or the address of the selected memory cell is within a far cell group arranged far from the control circuit block.

13. The resistance variable memory device of claim 11 , wherein the control circuit block further comprises a control signal generation circuit for logically combining the detection signal with the address information of the selected memory cell to generate a control signal for enabling the high resistance path circuit and the bypass circuit of the write pulse control block.

14. The resistance variable memory device of claim 11 , further comprising a position storage block configured to classify the plurality of memory cells into a near cell group and a far cell group,
wherein the near cell group includes memory cells having a first error ratio while being positioned near to the control circuit block, and
the far cell group includes memory cells having a second error ratio lower than the first error ratio while being positioned far from the control circuit block.

15. The resistance variable memory device of claim 11 , wherein the high resistance path circuit comprises a MOS transistor, and the MOS transistor of the high resistance path circuit has a resistance higher than a resistance of when the bypass circuit is selected and lower than a resistance of when the bypass circuit is not selected.

16. The resistance variable memory device of claim 11 , wherein the high resistance path circuit comprises a variable resistance, and the variable resistance is higher than a resistance of when the bypass circuit is selected and lower than a resistance of when the bypass circuit is not selected.

17. The resistance variable memory device of claim 11 , wherein the high resistance path circuit comprises a plurality

Assignees

• Sk Hynix Inc

Inventors

• Lee Ki Won
• Park Jin Su

Classifications

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C13/0038

  Power supply circuits · CPC title

• G11C13/0028 Primary

  Word-line or row circuits · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title