Mitigating read disturb in a cross-point memory

Patent metadata

Field	Value
Publication number	US-9286975-B2
Application number	US-201414204376-A
Country	US
Kind code	B2
Filing date	Mar 11, 2014
Priority date	Mar 11, 2014
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.

First claim

What is claimed is:

1. An apparatus comprising:
a memory controller configured to select a target memory cell for a memory access operation, the memory controller comprising:
a sense module configured to determine whether a snap back event occurs during a sensing interval of a read completion time interval; and
a write back module configured to write back, during said read completion time interval, a logic one to the memory cell in response to a snap back event being detected during said read completion time interval; and

switch circuitry comprising a word line (WL) switch configured to couple a target WL to a WL select voltage source, and a bit line (BL) switch configured to couple a target BL to a BL select voltage source;
wherein the memory controller is configured to control the switch circuitry to turn at least one of the WL switch or the BL switch partially OFF at or near the start of the sensing interval and to turn said at least one of the WL switch or the BL switch ON in response to a snap back event being detected during said read completion time interval.

2. The apparatus of claim 1 , wherein the memory controller is controller configured to control the switch circuitry to turn the WL switch and the BL switch ON prior to a start of the sensing interval.

3. The apparatus of claim 1 , wherein the memory controller is configured to output a logic one if a snap back event is detected.

4. The apparatus of claim 1 , wherein the memory controller is configured to output a logic zero if a snap back event is not detected.

5. A method comprising:
selecting, by a memory controller, a target memory cell for a memory access operation;
determining, by a sense module, whether a snap back event occurs during a sensing interval of a read completion time interval;
writing back, by a write back module during said read completion time interval, a logic one to the memory cell in response to a snap back event being detected during said read completion time interval;
controlling, by the memory controller, switch circuitry to turn at least one of a WL switch or a BL switch partially OFF at or near the start of the sensing interval; and
controlling, by the memory controller, the switch circuitry to turn said at least one of the WL switch or the BL switch ON in response to a snap back event being detected during said read completion time interval.

6. The method of claim 5 , further comprising:
controlling, by the memory controller, the switch circuitry to turn a word line (WL) switch and a bit line (BL) switch ON prior to a start of the sensing interval.

7. The method of claim 5 , further comprising:
outputting, by the memory controller, a logic one if a snap back event is detected.

8. The method of claim 5 , further comprising:
outputting, by the memory controller, a logic zero if a snap back event is not detected.

9. A system comprising:
a processor;
a cross-point memory array comprising a target memory cell, a target word line (WL) and a target bit line (BL), the target memory cell coupled between the target WL and the target BL;
a memory controller coupled to the processor and the cross-point memory array, the memory controller configured to select a target memory cell for a memory access operation, the memory controller comprising:
a sense module configured to determine whether a snap back event occurs during a sensing interval of a read completion time interval; and
a write back module configured to write back, during said read completion time interval, a logic one to the memory cell in response to a snap back event being during said read completion time interval; and

switch circuitry comprising a word line (WL) switch configured to couple a target WL to a WL select voltage source, and a bit line (BL) switch configured to couple a target BL to a BL select voltage source;
wherein the memory controller is configured to control the switch circuitry to turn at least one of the WL switch or the BL switch partially OFF at or near the start of the sensing interval and to turn said at least one of the WL switch or the BL switch ON in response to a snap back event being detected during said read completion time interval.

10. The system of claim 9 , wherein the memory controller is controller configured to control the switch circuitry to turn the WL switch and the BL switch ON prior to a start of the sensing interval.

11. The system of claim 9 , wherein the memory controller is configured to output a logic one if a snap back event is detected.

12. The system of claim 9 , wherein the memory controller is configured to output a logic zero if a snap back event is not detected.

Assignees

• Intel Corp

Inventors

• Chu Daniel J
• Pangal Kiran
• Franklin Nathan R
• Damle Prashant S
• Chaohong Hu

Classifications

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title

• G11C13/0035

  Evaluating degradation, retention or wearout, e.g. by counting writing cycles · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0033

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title