Phase change memory current

Patent metadata

Field	Value
Publication number	US-9792986-B2
Application number	US-201514725826-A
Country	US
Kind code	B2
Filing date	May 29, 2015
Priority date	May 29, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.

First claim

What is claimed is:

1. An apparatus comprising:
a memory controller comprising a word line (WL) control module and a bit line (BL) control module, the memory controller to initiate selection of a memory cell in a phase change memory; and
a mitigation module to configure a first line selection logic to reduce transient energy dissipation related to snap back occurring when selecting the memory cell by:
enabling a selection current source to provide a selection current greater than or equal to a hold current associated with the memory cell,
configuring the first line selection logic to increase an allowable current to the memory cell by decreasing a drain-source resistance for at least one MOSFET in a current path and enable a pulse current source to provide a pulse current to at least one of read from or program the memory cell, and
disabling the selection current source when the pulse current source is enabled.

2. The apparatus of claim 1 , wherein the first line selection logic is to select a word line.

3. The apparatus of claim 1 , wherein the first line selection logic is to select a bit line.

4. The apparatus of claim 1 , wherein the selection current source is a constant current source.

5. The apparatus of claim 1 further comprising a line path capacitance associated with the first line selection logic and the selection current source.

6. The apparatus of claim 5 wherein initiating selection of a memory cell includes charging said line path capacitance to a charge and voltage related to a first bias voltage.

7. A method comprising:
initiating, by a memory controller, selection of a memory cell in a phase change memory; and
configuring, by a mitigation module, a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to snap back occurring when selecting the memory cell; enabling, by the mitigation module, a selection current source to provide a selection current, the selection current greater than or equal to a hold current associated with the memory cell; configuring, by the mitigation module, the first line selection logic to increase an allowable current to the memory cell by decreasing a drain-source resistance for at least one MOSFET in a current path; enabling, by the mitigation module, a pulse current source to provide a pulse current to the memory cell, the pulse current to at least one of read from or program the memory cell; and disabling, by the mitigation module, a selection current source when the pulse current source is enabled.

8. The method of claim 7 , wherein the first line selection logic is to select a word line.

9. The method of claim 7 , wherein the first line selection logic is to select a bit line.

10. The method of claim 7 , wherein the selection current source is a constant current source.

11. The method of claim 7 further comprising controlling a line path capacitance associated with the first line selection logic and the selection current source.

12. The method of claim 11 wherein initiating selection of a memory cell includes charging said line path capacitance to a charge and voltage related to a first bias voltage.

13. A system comprising:
a processor;
a cross-point memory array comprising a memory cell in a phase change memory, a word line (WL) and a bit line (BL), the memory cell coupled between the word line and the bit line; and
a memory controller to initiate selection of a target memory cell, the memory controller comprising:
a WL control module and a BL control module, and
a mitigation module to configure a first line selection logic to reduce transient energy dissipation related to snap back occurring when selecting the memory cell by enabling a selection current source to provide a selection current greater than or equal to a hold current associated with the memory cell, configuring the first line selection logic to increase an allowable current to the memory cell by decreasing a drain-source resistance for at least one MOSFET in a current path and enable a pulse current source to provide a pulse current to at least one of read from or program the memory cell, and disabling the selection current source when the pulse current source is enabled.

14. The system of claim 13 , wherein the first line selection logic is to select a word line.

15. The system of claim 13 , wherein the first line selection logic is to select a bit line.

16. The system of claim 13 , wherein the selection current source is a constant current source.

17. The system of claim 13 further comprising controlling a line path capacitance associated with the first line selection logic and the selection current source.

18. The system of claim 17 wherein initiating selection of a memory cell includes charging said line path capacitance to a charge and voltage related to a first bias voltage.

Assignees

• Intel Corp

Inventors

• Taub Mase J
• Guliani Sandeep K
• Pangal Kiran
• Zeng Raymond W

Classifications

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title