Out-of-bounds recovery circuit

Patent metadata

Field	Value
Publication number	US-11030039-B2
Application number	US-202017028253-A
Country	US
Kind code	B2
Filing date	Sep 22, 2020
Priority date	Oct 14, 2016
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

First claim

What is claimed is:

1. An out-of-bounds recovery circuit for an electronic device having at least a first operating state having first non-allowable memory addresses and a second operating state having second non-allowable memory addresses, the out-of-bounds recovery circuit comprising:
detection logic configured to:
monitor one or more control and/or data signals of the electronic device,
detect an out-of-bounds violation in the electronic device, when the detection logic determines, based on the one or more control and/or data signals of the electronic device, that the electronic device is in the first operating state and a processing element of the electronic device has fetched an instruction from one of the first non-allowable memory addresses, and
detect an out-of-bounds violation in the electronic device, when the detection logic determines, based on the one or more control and/or data signals of the electronic device, that the electronic device is in the second operating state and the processing element of the electronic device has fetched an instruction from one of the second non-allowable memory addresses; and

transition logic configured to, in response to the detection logic detecting an out-of-bounds violation, cause the electronic device to transition to a predetermined safe state.

2. The out-of-bounds recovery circuit of claim 1 , wherein the one or more control and/or data signals includes a signal indicating a current value of a program counter of the processing element, and the detection logic is configured to determine that the processing element has fetched an instruction from one of the first non-allowable memory addresses when the current value of the program counter does not fall within at least one allowable memory address range for the first operating state of the electronic device.

3. The out-of-bounds recovery circuit of claim 1 , wherein the first operating state is a boot operating state in which the electronic device executes boot firmware.

4. The out-of-bounds recovery circuit of claim 1 , wherein the first operating state is associated with one or more first allowable memory address ranges and the second operating state is associated with one or more second allowable memory address ranges.

5. The out-of-bounds recovery circuit of claim 4 , wherein the detection logic comprises address range generator logic configured to identify the one or more first allowable memory address ranges and the one or more second allowable memory address ranges.

6. The out-of-bounds recovery circuit of claim 4 , wherein the one or more control and/or data signals includes one or more signals indicating a current operating state of the electronic device.

7. The out-of-bounds recovery circuit of claim 6 , wherein the first operating state is a boot operating state and the second operating state is a normal operating state, and the one or more signals indicating the current operating state of the electronic device comprises a signal indicating whether a power on sequence is complete.

8. The out-of-bounds recovery circuit of claim 7 , wherein the detection logic is configured to determine that the electronic device is in the boot operating state when the power on sequence is not complete and determine that the electronic device is in the normal operating state when the power on sequence is complete.

9. The out-of-bounds recovery circuit of claim 1 , wherein the detection logic comprises an out-of-bounds violation detected register, and the detection logic is configured to, in response to detecting an out-of-bounds violation, set the out-of-bounds violation detected register; and the transition logic is configured to determine that the detection logic has detected an out-of-bounds violation based on the out-of-bounds violation detected register.

10. The out-of-bounds recovery circuit of claim 1 , wherein the detection logic is configured to, in response to detecting an out-of-bounds violation, generate a signal indicating that the detection logic has detected an out-of-bounds violation, and the transition logic is configured to determine whether the detection logic has detected an out-of-bounds violation based on the generated signal.

11. The out-of-bounds recovery circuit of claim 1 , wherein the transition logic is configured to cause the electronic device to transition to the predetermined safe state by setting the state of the processing element to a particular state.

12. The out-of-bounds recovery circuit of claim 11 , wherein the particular state is an idle state.

13. The out-of-bounds recovery circuit of claim 1 , wherein the transition logic is configured to cause the electronic device to transition to a predetermined safe state by invoking an interrupt.

14. The out-of-bounds recovery circuit of claim 1 , wherein the transition logic is further configured to, in response to the detection logic detecting an out-of-bounds violation, invalidate the fetched instruction so that the processing element does not execute the instruction fetched from the non-allowable memory address.

15. The out-of-bounds recovery circuit of claim 1 , wherein the out-of-bounds recovery circuit is embodied in hardware on an integrated circuit.

16. An electronic device comprising a processing element and the out-of-bounds recovery circuit as set forth in claim 1 .

17. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture the out-of-bounds recovery circuit as set forth in claim 1 .

18. A method of recovering an electronic device from an out-of-bounds violation, the electronic device having at least a first operating state having first non-allowable memory addresses and a second operating state having second non-allowable memory addresses, the method comprising:
monitoring, by an out-of-bounds recovery circuit, one or more control and/or data signals of the electronic device;
detecting, by the out-of-bounds recovery circuit, an out-of-bounds violation in the electronic device when it is determined, from the one or more control and/or data signals of the electronic device, that the electronic device is in the first operating state and a processing element of the electronic device has fetched an instruction from one of the first non-allowable memory addresses;
detecting, by the out-of-bounds recovery circuit, an out-of-bounds violation in the electronic device when it is determined, from the one or more control and/or data signals of the electronic device, that the electronic device is in the second operating state and the processing element of the electronic device has fetched an instruction from one of the second non-allowable memory addresses; and
in response to detecting an out-of-bounds violation, causing, by the out-of-bounds recovery circuit, the electronic device to transition to a predetermined safe state.

19. The method of claim 18 , wherein the one or more control and/or data signals includes a signal indicating a current value of a program counter of the processing element, and it is determined that the processing element has fetched an instruction from one of the first non-allowable memory addresses when the current value of the program counter does not fall within at least one allowable memory address range for the first operating state of the electronic device.

20. A non-transitory computer readable storage medium havi

Assignees

• Imagination Tech Ltd

Inventors

• Darbari Ashish
• Singleton Iain

Classifications

• G06F21/52

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F30/30 Primary

  Circuit design · CPC title

• G06F11/0736

  in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function (testing or monitoring of automated control systems G05B23/02) · CPC title

• G06F21/74

  operating in dual or compartmented mode, i.e. at least one secure mode · CPC title