Methods and systems for transitioning between a user state and a supervisor state based on a next instruction fetch address

Patent metadata

Field	Value
Publication number	US-9672164-B2
Application number	US-201213485078-A
Country	US
Kind code	B2
Filing date	May 31, 2012
Priority date	May 31, 2012
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.

First claim

What is claimed is:

1. A processing system comprising:
data memory having a first data memory region allocated to first data associated with a first privilege state, and a second data memory region allocated to second data associated with a second privilege state, wherein the first data memory region includes a first stack region within which a first stack is maintained, and the second data memory region includes a second stack region within which a second stack is maintained;
code memory having a first code memory region allocated to first computer instructions associated with the first privilege state, and a second code memory region allocated to second computer instructions associated with the second privilege state;
a peripheral module that includes a set of protection registers, wherein the set of protection registers includes
at least one code address register that stores at least one instruction address range indicator, wherein the at least one instruction address range indicator indicates boundaries of the first code memory region and the second code memory region, and
an alternate stack pointer register configured to store a first address that corresponds to a top element of the first stack when a current privilege state is the second privilege state, or to store a second address that corresponds to a top element of the second stack when the current privilege state is the first privilege state; and

a processor core that accesses the peripheral module over a system bus, wherein the processor core includes
a stack pointer configured to store the first address that corresponds to the top element of the first stack when the current privilege state is the first privilege state, or to store the second address that corresponds to the top element of the second stack when the current privilege state is the second privilege state,
first circuitry configured to determine, by comparing a third address of an instruction fetched from the code memory with the at least one instruction address range indicator in the set of protection registers, whether the current privilege state is the first privilege state or the second privilege state, and
second circuitry configured to determine whether a next instruction fetch address corresponds to a first memory location within a code memory region associated with the current privilege state or to a second memory location within a code memory region associated with a different privilege state by comparing the next instruction fetch address with the at least one instruction address range indicator in the set of protection registers, and when the next instruction fetch address is not within the first code memory region associated with the current privilege state, to allow a next computer instruction stored at the next instruction fetch address to be fetched only when a transition from the current privilege state to the different privilege state is legal, and when the transition from the current privilege state to the different privilege state is performed, to swap an address stored in the stack pointer with an address stored in the alternate stack pointer register.

2. The processing system of claim 1 , wherein the first privilege state is a supervisor state having a first privilege level, and the second privilege state is a user state having a second privilege level that is lower than the first privilege level.

3. The processing system of claim 1 , wherein:
the at least one instruction address range indicator defines a supervisor code memory region allocated for storing supervisor code associated with a supervisor state and defines a user code memory region allocated for storing user code associated with a user state, and
the second circuitry is configured to determine that the next instruction fetch address is within a code memory region associated with the supervisor state when the next instruction fetch address falls within the supervisor code memory region, and the next instruction fetch address is within a code memory region associated with the user state when the next instruction fetch address falls within the user code memory region.

4. The processing system of claim 1 , wherein:
the second circuitry is further configured to produce a fault and disallow the next computer instruction from being fetched when the transition from the current privilege state to the different privilege state is not legal.

5. The processing system of claim 1 , further comprising:
at least one data address register in the peripheral module, wherein the at least on data address register stores at least one data address range indicator, wherein the at least one data address range indicator indicates boundaries of the first data memory region and the second data memory region; and
third circuitry configured to determine that a data access address is generated for a computer instruction, to determine whether the data access address is associated with the first privilege state or with the second privilege state by comparing the data access address with the at least one data address range indicator in the peripheral module, and to allow access to a third memory location corresponding to the data access address when the current privilege state is a privilege state in which access to the third memory location is allowed.

6. The processing system of claim 5 , wherein:
the at least one data address range indicator defines the first data memory region and one or more third data memory regions allocated for storing data associated with the first privilege state and defines the second data memory region and one or more fourth data memory regions allocated for storing data associated with the second privilege state, and
the third circuitry is configured to determine that the data access address is associated with the first privilege state when the data access address falls within one of the first data memory region or the one or more third data memory regions, and the data access address is associated with the second privilege state when the data access address falls within one of the second data memory region or the one or more fourth data memory regions.

7. The processing system of claim 5 , wherein the at least one data address range indicator defines the first data memory region and the second data memory region.

8. The processing system of claim 5 , wherein:
the third circuitry is further configured to produce a fault and prohibit access to the third memory location corresponding to the data access address when the current privilege state is a privilege state in which access to the third memory location is not allowed.

9. A processing method comprising:
storing, in a peripheral module, at least one data address range indicator that defines one or more first data memory regions within data memory that are allocated to first data associated with a first privilege state, and defines one or more second data memory regions within the data memory that are allocated to second data associated with a second privilege state, wherein the one or more first data memory regions include a first stack region within which a first stack is maintained, and the one or more second data memory regions include a second stack region within which a second stack is maintained;
storing, in the peripheral module, at least one instruction address range indicator that defines one or more first code memory regions allocated for storing computer instructions associated with the first privilege state and that defines one or more second code memory regions allocated for storing computer instructions associated with the second privilege state;
defining a current privilege state as the first privilege state or the second privilege state based on a first ad

Assignees

• Mccarthy Daniel M
• Circello Joseph C
• Hausman Kristen A
• Nxp Usa Inc

Inventors

• Mccarthy Daniel M
• Circello Joseph C
• Hausman Kristen A

Classifications

• G06F12/023

  Free address space management · CPC title

• G06F9/3802

  Instruction prefetching · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F12/1441

  for a range · CPC title