Comparator circuit and mobile device

Patent metadata

Field	Value
Publication number	US-11025241-B2
Application number	US-201916704898-A
Country	US
Kind code	B2
Filing date	Dec 5, 2019
Priority date	Dec 20, 2018
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A comparator circuit includes a differential input circuit, a load circuit, a first current source, a first bias voltage supplying circuit, a third connection circuit, and a fourth connection circuit. The differential input circuit includes a first transistor to which a first input signal is supplied and a second transistor to which a second input signal is supplied. The load circuit includes a third transistor connected to the first transistor through a first connection circuit and a fourth transistor connected to the second transistor through a second connection circuit, gates of the third and fourth transistors being connected to the first connection circuit through a third capacitor. The first bias voltage supplying circuit supplies a first bias voltage to the gates of the third and fourth transistors and the third capacitor.

First claim

What is claimed is:

1. A comparator circuit comprising:
a differential amplifier configured to compare a first input signal and a second input signal to output a comparison result; and
an output amplifier configured to output an amplified signal based on the comparison result,
wherein the differential amplifier comprises:
a differential input circuit including a first transistor and a second transistor, the first input signal being applied to a gate of the first transistor through a first capacitor and the second input signal being supplied to a gate of the second transistor through a second capacitor;
a load circuit providing a load to the differential input circuit and including a third transistor connected to the first transistor with a first connection circuit interposed therebetween and a fourth transistor connected to the second transistor with a second connection circuit interposed therebetween, gates of the third transistor and the fourth transistor being connected to the first connection circuit through a third capacitor;
a first current source being a current source of the differential input circuit and connected to the first transistor and the second transistor;
a first bias voltage supplying circuit supplying a first bias signal different from the first and second input signals to the gates of the third transistor and the fourth transistor and the third capacitor, the first bias signal including a first bias voltage;
a second bias voltage supplying circuit supplying a second bias signal to the first connection circuit;
a third connection circuit connecting the gate of the first transistor and the first connection circuit;
a fourth connection circuit connecting the gate of the second transistor and the second connection circuit; and
a switch for adjusting a timing to supply the second bias voltage to the first connection circuit,
wherein the output amplifier comprises:
a fifth transistor comprising a gate supplied with a signal based on the comparison result through a fourth capacitor;
a second current source connected to the fifth transistor with a fifth connection circuit interposed therebetween;
a sixth connection circuit connecting a gate of the fifth transistor and the fifth connection circuit; and
an output part disposed in the fifth connection circuit and outputting the amplified signal.

2. The comparator circuit of claim 1 , wherein the first bias voltage supplying circuit includes a first switch for adjusting a timing to supply the first bias voltage, wherein the third connection circuit includes a second switch for adjusting a timing to connect the gate of the first transistor and the first connection circuit, wherein the fourth connection circuit includes a third switch for adjusting a timing to connect the gate of the second transistor and the second connection circuit, and wherein the sixth connection circuit includes a fourth switch for adjusting a timing to connect the gate of the fifth transistor and the fifth connection circuit.

3. The comparator circuit of claim 2 , wherein the first switch is turned on before the second switch, the third switch, the fourth switch, and the fifth switch are turned on, wherein the fifth switch, the second switch, the third switch, and the fourth switch are turned on at a same time, and wherein the second switch, the third switch, and the fourth switch are turned off after the first switch and the fifth switch are turned off.

4. The comparator circuit of claim 2 , wherein the differential amplifier further comprises:
a buffer circuit connected between the first capacitor and the gate of the first transistor,
wherein the buffer circuit comprises:
a constant current supplying circuit supplying a given current;
a buffer transistor having a source, a drain, and a gate, one of the source and the drain is connected to the constant current supplying circuit, the other thereof is connected to a ground, and the first input signal and a second bias voltage are supplied to the gate; a second bias voltage supplying circuit supplying the second bias voltage; and
a sixth switch for adjusting a timing to supply the second bias voltage to the gate of the buffer transistor.

5. The comparator circuit of claim 4 , wherein the second switch, the third switch, and the fourth switch are turned on after the first switch and the sixth switch are turned on and are turned off after the first switch and the sixth switch are turned off.

6. The comparator circuit of claim 2 , wherein each of the first current source and the second current source includes a current source transistor, a gate of the current source transistor is supplied with a third bias voltage.

7. The comparator circuit of claim 6 , wherein each of the first current source and the second current source further comprises a current source switch for adjusting a timing to supply the third bias voltage.

8. The comparator circuit of claim 7 , wherein the current source switch is turned off when the first switch is being turned off.

9. A mobile device comprising an analog-to-digital converter (ADC) circuit comprising a plurality of the comparator circuit, wherein each of the plurality of the comparator circuit comprises:
a differential amplifier configured to compare a first input signal and a second input signal to output a comparison result; and
an output amplifier configured to output an amplified signal based on the comparison result,
wherein the differential amplifier comprises:
a differential input circuit including a first transistor and a second transistor, the first input signal being applied to a gate of the first transistor through a first capacitor and the second input signal being supplied to a gate of the second transistor through a second capacitor;
a load circuit providing a load to the differential input circuit and including a third transistor connected to the first transistor with a first connection circuit interposed therebetween and a fourth transistor connected to the second transistor with a second connection circuit interposed therebetween, gates of the third transistor and the fourth transistor being connected to the first connection circuit through a third capacitor;
a first current source being a current source of the differential input circuit and connected to the first transistor and the second transistor;
a first bias voltage supplying circuit supplying a first bias voltage to the gates of the third transistor and the fourth transistor and the third capacitor;
a fourth capacitor connected to the second connection circuit and configured to output the comparison result;
a third connection circuit connecting the gate of the first transistor and the first connection circuit; and
a fourth connection circuit connecting the gate of the second transistor and the second connection circuit,
wherein the output amplifier comprises:
a fifth transistor comprising a gate connected to a terminal of the fourth capacitor;
a second current source connected to the fifth transistor with a fifth connection circuit interposed therebetween;
a sixth connection circuit connecting a gate of the fifth transistor and the fifth connection circuit; and
an output part disposed in the fifth connection circuit and outputting the amplified signal.

10. The mobile device of claim 9 , comprises a semiconductor device, wherein the semiconductor device comprises:
the ADC circuit; and
a plurality of photoelectric conversion elements arranged in a matrix shape, wherein the ADC circuit performs discrete processing on an analog signal generated by the photoelectric conversion elements.

11. The mobile device of claim 9 , further comprises a lens for imaging a picture of a sub

Assignees

• Samsung Electronics Co Ltd

Inventors

• Nakatsuka Shinji
• Mishina Koji
• Fukushima Noriyuki

Classifications

• H03K5/249 Primary

  using clock signals · CPC title

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H03M1/129

  Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling (H03M1/18 takes precedence); Out-of-range indication · CPC title