Imaging device for reducing deterioration of A/D conversion accuracy

Patent metadata

Field	Value
Publication number	US-9918032-B2
Application number	US-201615260954-A
Country	US
Kind code	B2
Filing date	Sep 9, 2016
Priority date	Mar 17, 2014
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

An imaging device includes: an imaging section in which a plurality of pixels each having a photoelectric conversion element are arranged in a matrix shape; a clock generator that generates a plurality of phase signals having different phases; a reference signal generator that generates a reference signal which increases or decreases with a lapse of time; a comparator that is disposed to correspond to each column of an array of the plurality of pixels, performs a comparing process of comparing a pixel signal output from each pixel with the reference signal, and outputs a first comparison result signal and a second comparison result signal indicating a result of the comparing process; a latch section that is disposed to correspond to the comparator and latches logic states of the plurality of phase signals; and a latch controller.

First claim

What is claimed is:

1. An imaging device comprising:
an imaging section in which a plurality of pixels each having a photoelectric conversion element are arranged in a matrix shape;
a clock generator that generates a plurality of phase signals having different phases;
a reference signal generator that generates a reference signal which increases or decreases with a lapse of time;
a comparator that is disposed to correspond to each column or columns of an array of the plurality of pixels, performs a comparing process of comparing a pixel signal output from each pixel with the reference signal, and outputs a first comparison result signal and a second comparison result signal indicating a result of the comparing process;
a latch section that is disposed to correspond to the comparator and latches logic states of the plurality of phase signals; and
a latch controller that is disposed to correspond to the comparator, activates the latch section depending on a comparison result indicated by the first comparison result signal, and causes the latch section to perform a latching operation depending on a comparison result indicated by the second comparison result signal,
wherein the comparator includes:
a differential amplifier that includes a first transistor to a gate of which the reference signal is input and a second transistor to a gate of which the pixel signal is input, outputs a standard signal at a time of initialization of voltages of the gate of the first transistor and the gate of the second transistor, and outputs a first comparison signal corresponding to a result of comparing the reference signal with the pixel signal at a time of performing the comparing process;
a third transistor that is a transistor operating as a constant current source, has a source electrically connected to a voltage source, and outputs a current at the time of performing the comparing process; and
a first capacitive element that has a first terminal electrically connected to a gate of the third transistor and a second terminal electrically connected to the voltage source, samples a standard voltage based on the standard signal at the time of the initialization, and outputs the standard voltage to the first terminal at the time of performing the comparing process,
the first comparison result signal is generated from the first comparison signal,
the second comparison result signal is generated from an output of a drain of the third transistor, and
a timing at which a state of the second comparison result signal is changed is later than a timing at which a state of the first comparison result signal is changed,
the comparator further includes:
a first switching element that electrically connects the gate and a drain of the first transistor at the time of the initialization and electrically disconnects the gate and the drain of the first transistor at the time of performing the comparing process;
a second switching element that electrically connects the gate and a drain of the second transistor at the time of the initialization and electrically disconnects the gate and the drain of the second transistor at the time of performing the comparing process;
a second capacitive element that has a first terminal electrically connected to the gate of the first transistor and a second terminal to which the reference signal is input and samples a voltage of the drain of the first transistor at the time of the initialization; and
a third capacitive element that has a first terminal electrically connected to the gate of the second transistor and a second terminal to which the pixel signal is input and samples a voltage of the drain of the second transistor at the time of the initialization, wherein the first transistor and the second transistor are transistors of a first conductivity type,
the third transistor is a transistor of a second conductivity type,
the comparator includes:
a fourth transistor of the first conductivity type, to a gate of which the standard signal and the first comparison signal are input;
a fifth transistor of the first conductivity type, whose drain is electrically connected to a source of the fourth transistor;
a sixth transistor of the first conductivity type, to a gate of which a signal output from a junction point of the fourth transistor and the fifth transistor is input and a drain thereof is electrically connected to the drain of the third transistor; and
a third switching element that electrically connects the drain of the third transistor and the first terminal of the first capacitive element at the time of the initialization and electrically disconnects the drain of the third transistor and the first terminal of the first capacitive element at the time of performing the comparing process,
the first capacitive element samples the standard voltage which is a voltage of the drain of the third transistor at the time of the initialization, and
the second comparison result signal is output from a junction point of the third transistor and the sixth transistor.

2. An imaging device comprising:
an imaging section in which a plurality of pixels each having a photoelectric conversion element are arranged in a matrix shape;
a clock generator that generates a plurality of phase signals having different phases;
a reference signal generator that generates a reference signal which increases or decreases with a lapse of time;
a comparator that is disposed to correspond to each column or columns of an array of the plurality of pixels, performs a comparing process of comparing a pixel signal output from each pixel with the reference signal, and outputs a first comparison result signal and a second comparison result signal indicating a result of the comparing process;
a latch section that is disposed to correspond to the comparator and latches logic states of the plurality of phase signals; and
a latch controller that is disposed to correspond to the comparator, activates the latch section depending on a comparison result indicated by the first comparison result signal, and causes the latch section to perform a latching operation depending on a comparison result indicated by the second comparison result signal,
wherein the comparator includes:
a differential amplifier that includes a first transistor to a gate of which the reference signal is input and a second transistor to a gate of which the pixel signal is input, outputs a standard signal at a time of initialization of voltages of the gate of the first transistor and the gate of the second transistor, and outputs a first comparison signal corresponding to a result of comparing the reference signal with the pixel signal at a time of performing the comparing process;
a third transistor that is a transistor operating as a constant current source, has a source electrically connected to a voltage source, and outputs a current at the time of performing the comparing process; and
a first capacitive element that has a first terminal electrically connected to a gate of the third transistor and a second terminal electrically connected to the voltage source, samples a standard voltage based on the standard signal at the time of the initialization, and outputs the standard voltage to the first terminal at the time of performing the comparing process,
the first comparison result signal is generated from the first comparison signal,
the second comparison result signal is generated from an output of a drain of the third transistor, and
a timing at which a state of the second comparison result signal is changed is later than a timing at which a state of the first comparison result signal is changed,
the comparator further includes:
a first switching element that electrically connects the gate and a drain of the first transistor at the time of the initialization and electrically disconnects the gate and the drain of t

Assignees

• Olympus Corp

Inventors

• Hagihara Yoshio

Classifications

• H04N25/778 Primary

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title

• H04N5/3765 Primary

  Electricity · mapped topic

• H04N5/378

  Electricity · mapped topic

• H04N5/37455

  Electricity · mapped topic